Hardware-Based Side

The technique is divided in software-based and hardware-based sides, which communicate through memory writes at predefined memory addresses. In order to do so, PODER exploits two main concepts ... 

PODER s hardware-based side aims at complementing the software-based side in detecting incorrect jumps to the beginning of a BB (1) and incorrect jumps to the same BB (2), but also detecting incorrect jumps to unused memory addresses (3), and control flow loops (4). 

OCFCM s hardware-based side aims at detecting faults that cause incorrect deviations in the execution program s flow. In order to do that, the hardware module combines most of the non-intrusive hardware-based techniques, such as checking if the processor is accessing correct memory areas for data and program, the consistency of some variables, control flow checkpoints, and also the PC evolution during runtime. 

Following the state-of-the-art review, the next step is to implement fault tolerance techniques. We will start by explaining in detail and implementing two known software-based techniques, called Variables and Inverted Branches (AZAMBUJA 2010b), which will later be used as a complement to hybrid fault tolerance techniques. These techniques have been proposed in the past years and achieved high fault detection rates at low performance degradation levels and therefore are useful not only as an introduction to software-based fault tolerance techniques, but also to be combined with hardware-based and hybrid techniques. Then, three novel hybrid techniques will be proposed and implemented, based on both software and hardware replication characteristics. The three hybrid techniques will be divided into their software and hardware sides and described in detail, concerning both operation description and implementation. 

OCFCM itself is defined as a non-intrasive hardware module and therefore corrld be considered a pure hardware-based technique. Irrstead, OCFCM alone cannot achieve its main objective, which is detecting control flow errors. To do so, it has to be complemented by the Inverted Branches software-based technique (described in Sect. 4.3) and configured by the apphcation running in the processor. Because of these characteristics, it is considered as a hybrid farrlt tolerant technique, even if not as tightly coupled with the software-side as PODER. 

In the next subsections, the terminology used for HETA is presented, as well as the hardware-based and software-based sides of the technique. 

The hardware module was implemented in VHDL language, based on a timer that signals an error if not reset. To calculate the XOR value, we added a 16-bit accumulator register that performs a XOR operation between its current and new values so that it is not only able to calculate the real-time XOR value, but also to stores it. A decoder was also added to identify instructions from the software-based side. 

Since supercritical fluids were chosen for their ability to penetrate small cracks and crevices, additional tests were performed to evaluate this characteristic. A test cube modeled after a similar fixture fiibricated by Ferranti Aerospace, was developed and manufactured to md in this study. The cube had a number of blind holes, tapped holes, dtannels and crevices to simulate actual hardware. Beryllium, 300 Series stainless steel and aluminum cubes were constructed to simulate the conunon metals found in the instrument. In addition, the sides of the cube were removable to facilitate deposition of the contaminants into these blind holes and crevices and later analysis of cleaning effectiveness. The base of the cube was equipped vrith a scanning electron microscope (SEM) mount so that the cube could be examined directly in the SEM. Figure 3 is a photograph of a test cube. Extensive evaluations with these test cubes indicated that supercritical fluids were indeed effective at removing contaminants from cracks and crewces. 

Like PODER and OCFCM, HETA can also detect control flow loops (4). In order to detect this kind of error, a watchdog timer is implemented. The counter is reset every time the software-based technique side enters a BB, by performing a Reset XOR instruction. When the counter overflows, an error is flagged. By doing so, the hardware module can detect a control flow loop that causes the execution flow to be stuck at a single instruction. 

Within the past decade much progress has also been made in experimental realizations of quantum computing hardware. Many architectures have been proposed based on a variety of physical hardware. On a small scale, quantum information has been stored and manipulated in superconducting quantum bits (qubits) [4,5], trapped ions [6,7], electron spins [8-11], nuclear spins in the liquid or solid state [12], and other systems. On the theoretical side, new quantum algorithms have recently been found, exhibiting significant pol momial speedups on quantum computers for solution of sparse linear equations or differential equations [13,14], quantum Monte Carlo problems [15], and classical simulated annealing problems [16]. 

On the hardware side, other speedup strategies are essentially based on the simple idea that since hardware is becoming less and less expensive, one may use many processing units instead of only one and split up the job. Parallelization and clustering strategies belong to this family either the central processors carry out many calculations at the same time, as in parallel machines, or physically separate machines actually load different parts of the total job, as happens in clusters, which may nowadays contain up to 50-100 computers. In both cases the big problem is the synchronization... 

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