Patterned Oxide Etch Back

Another established optimization technique is patterned oxide etch back [14]. Its purpose is to remove most of the oxide in active areas prior to CMP. An additional lithography step is performed in order to mask the isolation areas 

FIGURE 12.16 Schematic cross section of a wafer without optimization (above) and with dummy active area insertion optimization (below). 

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Unlike W plasma etch back process, the typical W CMP process usually removes the adhesion layer such as Ti/TiN or TiN during the primary polish. As a result, during the over polish step there is some oxide loss. Since the oxide deposition, planarization CMP (oxide CMP), and tungsten CMP steps are subsequent to each other, the oxide thickness profile could become worse further into the process flow. Therefore, the across-wafer non-uniformity of the oxide loss during W CMP process is one of the very important process parameters needs to be optimized. To determine the effect of the process and hardware parameters on the polish rate and the across-wafer uniformity, designed experiments were run and trends were determined using analysis of variance techniques. Table speed, wafer carrier speed, down force, back pressure, blocked hole pattern, and carrier types were examined for their effects on polish rate and across-wafer uniformity. The variable ranges encompassed by the experiments used in this study are summarized in Table I. 

DYCOstrate. A different approach to small via creation has been taken by Dyconex AG of Switzerland. After ground and power patterns are formed on the panel, and the panel is oxide-treated, polyimide-backed copper foil is laminated on the panel. Holes in the copper are formed by a chemical etching process, and the insulating polyimide material underneath the holes is removed by plasma etching. PWBs made in such a way are called DYCOstrate. In other, similar technologies, different dielectric materials are used, and they are removed by alkaUne solutions. The rest of the process is similar to that for SLC that is, holes are metallized and a thick copper deposition is made by electroless or galvanic plating, and the circuit pattern is formed by a tent-and-etch process (see Fig. 5.5). 

Figure 1.13 Patterned SOIMUMPS wafer. Through-wafer etches are performed from the front side of the wafer 10 or 25 pm deep to form device layer holes, and from the back side 400 pm deep to form through-wafer holes. Both etches stop on the buried oxide. (Reprinted with permission from MEMSCAP Inc.)...

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