Wafer carriers

Semiconductor industry, vacuum chamber applications clamp rings for gas plasma etching equipment, wafer retaining rings for gas plasma etching, wafer carriers, vacuum tips... 

Imperial Chemical Industries has introduced a new crystalline poly(ether ether ketone) (PEEK) (structure 4.78). Applications are for compressor plates, valve seats, thrust washers, bearing cages, and pump impellers. In the aerospace industry it is employed as aircraft fairing, fuel valves, and ducting. It is also used in the electrical industry as wire coating and semiconductor wafer carriers. 

Aside from the basic approach to polishing, the most critical component of a CMP tool is the wafer earrier. As with CMP tools, wafer carriers have evolved from roots in lens grinding and in the silicon wafer polishing industries to meet requirements specific to polishing silicon-based integrated circuits. 

Fig. 8. Wafer carrier with a floating carrier plate. Pneumatic pressure is applied through an inlet resulting in hydrostatic pressure directly against the wafer. There is not necessarily any independent retaining ring control.

Preston s equation indicates a pressure dependency and if the pressure distribution across the surface of the wafer is not uniform, one expects a wafer-level removal rate dependency. Runnels et al, for example, report a model incorporating pressure dependencies to account for wafer scale nonuniformity [42]. The distribution of applied force across the surface of the wafer is highly dependent on the wafer carrier design, and significant innovation in head design to achieve either uniform or controllable pressure distributions is an important area of development. 

Bhushan et al. [9] independently confirmed the lack of polishing activity due to hydrodynamic lubrication. The depth of the wafer carrier in CMP was adjusted so that samples either projected above the surface of the carrier (the normal case), were essentially coplanar with the carrier, or were recessed below the plane of the carrier. This produced wafer-pad lubrication film thicknesses of controlled dimension. For the case of a wafer recess of 75 um ( 3 X the lubrication film thickness reported in Ref. [7]), removal rate was negligibly small. 

Fig. 2. Illustration of a lopsided wafer on a carrier due to the poor rebuilding of the wafer carrier.

Fig. 10. Illustration of the polish pad surface profile created by the wafer carrier due to the polish (wear) rate being higher at the wafer edge than at the wafer center. An end effector can be used to compensate the profile if the duration vs position profile is set up correctly.

Individual wafer Infrared lamp Wafer carrier counter-rotation heating (SiC-coated graphite)... 

FIGURE 5 Schematic diagram of a typical large-scale horizontal gas foil Planetary MOCVD reactor chamber. The precursor gases are injected in the center of the rotating wafer carrier and the gas flows horizontally over the individually rotating wafers. 

Here x is the conversion of SiH4. combines the effect of the molar expansion in the deposition process as well as the change in the volumetric flow and the dispersion coefficient, D, with temperature. At low pressures and small Re in LPCVD reactors the dispersion occurs mainly by molecular diffusion, therefore, we have used (D/D0) = (T/T0)l 65. e is the expansion coefficient and the stoichiometry implies that e = (xi)q, the entrance mole fraction of SiH4. The expansion coefficient, e is introduced as originally described by Levenspiel (33) The two reaction terms refer to the deposition on the reactor wall and wafer carrier and that on the wafers, respectively. The remaining quantities in these equations and the following ones are defined at the end of the paper. The boundary conditions are equivalent to the well known Danckwerts1 boundary conditions for fixed bed reactor models. 

Typically, both the wafer carrier and platen are rotated in the same direction. A downforce is applied while the wafer carrier and platen are rotated on their own axes coc and co, respectively. The polishing slurry is dispensed from a tube located at the center of the pad, and as the platen rotates the slurry is transported between the wafer and the pad [3-6]. In addition to the rotary platform, an orbital design has also been implemented (Fig. 3.3) [2]. The operating principle for the orbital design is similar to the rotary platform, except that the polishing head and table are in orbital motion to each other. In addition, the slurry is usually delivered through the pad. 

Figure 3.6 shows several types of CMP tools that have so far appeared in the market. The drawing at the center of Fig. 3.6 represents a bare-bone model, which has one wafer carrier (head) on one table. The left-hand side shows a model that has multiple wafer carriers on one table in order to increase throughput, that is, a multicarrier model. The right-hand side shows a model with several single-headed tables, that is, multitable model. 

Wafvr carrier e(l)>c proltte Wafer carrier center profile ... 

Friction change detected by motor current [31 ] This is one of the most popular recess process methods. In the example of W CMP, friction forces differ for W metals, barrier metals such as Ti and/or TiN, and substrates. These friction differences can be detected by the motor current of a wafer carrier or a table. 

Figure 2.6 Schematic representation of a wafer polishing tool, (a) Polish table with wafer carrier assembly, (b) Schematic view of wafer-slurry-pad system.

Fig. I. Schematic diagram for the standard wafer carrier used in Strasbaugh 6DS-SP for this study.

Fig. 2. Schematic diagram for the fixed-ring ViPRR (Viable Pressure Retaining Ring) wafer carrier used in Strasbaugh 6DS-SP for this study. Noticed the single piece retaining ring used in this type wafer carrier.

Unlike W plasma etch back process, the typical W CMP process usually removes the adhesion layer such as Ti/TiN or TiN during the primary polish. As a result, during the over polish step there is some oxide loss. Since the oxide deposition, planarization CMP (oxide CMP), and tungsten CMP steps are subsequent to each other, the oxide thickness profile could become worse further into the process flow. Therefore, the across-wafer non-uniformity of the oxide loss during W CMP process is one of the very important process parameters needs to be optimized. To determine the effect of the process and hardware parameters on the polish rate and the across-wafer uniformity, designed experiments were run and trends were determined using analysis of variance techniques. Table speed, wafer carrier speed, down force, back pressure, blocked hole pattern, and carrier types were examined for their effects on polish rate and across-wafer uniformity. The variable ranges encompassed by the experiments used in this study are summarized in Table I. 

Table II. General process trends for W CMP for ViPRR type wafer carrier. Up arrows mean that the parameter increases as a function of an increase in the process variable.

Table IV. Normalized die sort yield comparison for standard FetNOs) 3 (W2000) slurry with standard wafer carriers on Strasbaugh and new KI03 (MSW2000) slurry with the ViPRR type wafer carriers.

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