Chip placement

Magnetic field sensor Flow sensor Pressure sensor 

Wire bonding and the flip-chip technique are suitable for mechanically and electrically connecting the siiicon chip to the MID substrate with appropriate protection against environmental influences (Fig. 5.18). The technique of wire bonding 

UF = underfill, SM = substrate metallization, UBM = under-bump metallization 

FIGURE 5.18 Schematic view of relevant chip placement technologies for MID [63, 191] 

FIGURE 5.19 Elevated stress on connecting structures at the edges of the silicon chip [67, 138] 

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For the most part, PCs today use memory chips arranged on a small circuit board. These circuit boards are called Single Inline Memory Modules (SIMMs) or Dual Inline Memory Modules (DIMMs), depending on if there are chips on one side of the circuit board or on both sides, respectively. Aside from the difference in chip placement, memory modules also differ on the number of conductors, or pins, that the particular memory module uses. Some common examples include 30-pin, 72-pin andl68-pin (the latter two are most often DIMMs). Additionally, laptop memory comes in smaller form factors known as Small Outline DIMMs (SODIMMs). Figure 2.6 shows the popular form factors for the most popular memory chips. Notice how they basically look the same, but the memory module sizes are different. 

Listed in Table 40.3 are general performance characteristics for turret chip placement technology. This technology is constantly addressing smaller passive devices (0101 and 01005) as... 

TABLE 40.3 Capabilities of Turret Chip Placement Technology... 

Broadly speaking, the connection mediums and techniques familiar from conventional printed-circuit hoard technology can be used for mechanically locating and electrically contacting electronic components on MID. Soldering, conductive-adhesive gluing, bonding, and flip-chip placement are all in successful use under series-production conditions. 

Two important terms used to describe additives in polymeric mixtures are distribution and "dispersion . When mixing polymers with additives, we want to create a system in which the additive is both well distributed and dispersed. Distribution refers to the even placement of the additive throughout the polymer. For example, a well made batch of chocolate chip cookies has good distribution of the chips if every bite has a chocolate chip in it. A poorly distributed cookie would have all its chips on one side. Dispersion, on the other hand, refers to the separation of the individual components of a solid additive into its smallest parts. Figure 10.6 illustrates both good and bad distribution and dispersion. 

While polycarbonate has the desirable qualities as the basic material for information storage, it also has some debits. First, polycarbonate is relatively expensive in comparison with many polymers. Its superior combination of properties and ability for a large cost markup allows it to be an economically feasible material for specific commercial uses. Second, the polar backbone is susceptible to long-term hydrolysis so that water must be ruthlessly purged. The drying process, generally 4 h, is often achieved by placement of polycarbonate chips in an oven at 120°C with a dew point of — 18°C. 

During the replanting program, the oil palm trunks and fronds are chipped into small pieces and pulverized using a special pulverizer. The biomass residues are left in the field to allow for decomposition processing, which could then yield organic matter and release of plant nutrients. The placement of tmnk residues on field terraces could also reduce soil erosion. 

A HE FABRICATION OF INTEGRATED CIRCUITS involves a series of steps that defines insulator, conductor, and semiconductor structures in and on single crystals of silicon or gallium arsenide (I). As practiced today, the circuit elements are as small as 1 micrometer (1 xm) in dimension. Reproducible device performance and yield issues require control of both the dimension and placement of these 1-pm structures to tolerances of fractions of 1 xm. The number of such circuit elements per chip has steadily increased during the past three decades, mainly through a decrease in the size of the elements. This reduction in the feature size and the increase in circuit complexity and integration that it allows is largely responsible for the dramatic improvement in the performance and cost-performance ratio that has occurred and is expected to continue to occur. 

Keywords 2.5-D integration, placement, partition, mixed layout, standard cell, macro, wire length, inter-chip contact. 

The objective of the 2.5-D placement problem is to map a cell netlist (pure standard cell or mixed macro/standard cell) to unique positions in a layered space as illustrated in Fig. 6.1. The inter-chip contacts are assumed to be placed on top of the chip with no need to consume substrate area. We need to differentiate two scenarios hierarchical and flattened design styles. In a hierarchical design set up, after the floorplanning step, cells in a block need to be placed. As mentioned in the last chapter, a random-logic based block could be split into two chips. The 2.5-D placement problem is to assign the cells within such a block to unique positions on two chips. On the other hand, in a flattened design style, the 2.5-D placement problem is to place both standard cell macros onto stacked chips. 

In the following sections of this chapter, we studied the 2.5-D placement problem under the above mentioned three formulations pure standard cell designs with inter-chip contacts consuming substrate area, pure standard cell designs with inter-chip contacts on top of die surface, and mixed standard cell and macro designs corresponding to a flattened design style. 

In this section, we consider the second scenario of 2.5-D placement, where a hierarchical design style is applied and the inter-chip contacts can be placed above the top-level metal layer. 

In our placement experiments, we assume a fixed-die, over-the-cell routing model. Thus, the layout area of a design is the footprint of all cells plus 10% free space. The 2-D layout is mapped to a 2.5-D layout consisting of two stacking chips with equal area. All layouts have a square shape. Thus, the dimension of two chips in 2.5-D system is that of the corresponding 2-D layout scaled by 0.707. For every benchmark circuit, we generate both monolithic (2-D) placement and 2.5-D placement. 

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