Chip packaging

Fig. 2.2 Chip package with thermal conduction path to heat sink via TIMs. Reprinted from La-sance and Simons (2005) with permission...

Figure 7. Waveguide chip package of Texas Instruments.

The discrete microhotplates were packaged and bonded in a DIL-28 package for temperature sensor cahbration. A Pt-lOO-temperature sensor was attached to the chip package in close vicinity to the sensors. The chips were then caHbrated in an oven at temperatures up to 325 °C with the help of the Pt-100 resistor. A second-order polynomial was extracted from the measurements for each temperature sensor providing the temperature coefficients i and a2. ... 

With the conventional technology, ICs are mounted individually in plastic or ceramic single-chip packages (SCPs), such as dual-in-line packages (DIPs) or chip carriers, and the SCPs are interconnected on printed wiring boards (PWBs). The number of pins on SCPs has increased significantly, and line widths on PWBs, like IC feature sizes, have followed a historical downward trend (2). However, the basic SCP-on-PWB approach has remained predominant. 

Single-Chip Packaging. Dual-ln-Line Package. The predominant... 

Miura O (1995) Adhesives in Multiple Chip Packages. ACS Symposium, Pacifkhem 95, Honolulu... 

In a somewhat similar fashion, Ishii et alP- have demonstrated inkjet fabrication of polymeric microlenses for optical chip packaging. UV curable epoxy resin is deposited onto optical devices by inkjet printing. When the droplets hit the surface, they form into partial spheres due to their surface tension, and are UV-cured to form the microlens with diameters from 20 to 40 tm with /-numbers of 1.0 to 11.0. Their uniformity in a microlens array was measured to be within 1% in diameter and 3 tm in pitch (total count of 36 lenses). They have also demonstrated hybrid integration of inkjetted microlenses with a wire-bonded vertical-cavity-surface-emitting laser (VCSEL) with coupling efficiencies of 4 dB higher than without the microlens. 

Conventional single-chip packages have limited packing density on printed wiring boards (PWBs) and limit the system speed due to the large delay time for signals propagated between chips. 

Luo S, Wong CP. Surface property of passivation and solder mask for flip chip packaging. Proceedings of the IEEE Electronic Components and Technology Conference 2001. 

Computers, microprocessors, and other microelectronic devices could not exist as we know them today without the technology of depositing thin metal or alloy films with fine lithographic patterns. For example, in a computer, the individual transistors that make up an integrated circuit must be electrically interconnected by a complex network of conducting lines and vias that are deposited above the semiconductor layers. Furthermore, the chips are joined to multi-chip packaging modules, a process in which many electrical connections are simultaneously established by solder balls. 

Applications that have received attention, and the material properties that enable them, are shown in Figure 27.1. These applications are reviewed in detail in Waser and Ramesh. Decoupling capacitors and filters on semiconductor chips, packages, and polymer substrates (e.g., embedded passives ) utilize planar or low aspect ratio oxide films. These films, with thicknesses of 0.1 to 1 J,m, are readily prepared by CSD. Because capacitance density is a key consideration, high-permittivity materials are of interest. These needs may be met by morpho-tropic phase boundary PZT materials, BST, and BTZ (BaTi03-BaZr03) solid solutions. Phase shifters (for phase array antennas) and tunable resonator and filter applications are also enabled by these materials because their effective permittivity exhibits a dependence on the direct current (DC) bias voltage, an effect called tunability. 

Although the primary thermal transport mechanisms and the commonly used heat removal techniques vary substantially from one packaging level to the next, in general, heat removal can be addressed hierarchically. The first level of the hierarchy is at the chip package (IC) level where heat conducts from the chip or component to the package surfaces through interface materials and is then rejected from the outer surfaces (heat sink and the board) into ambient air (Figure 4). 

Typical systems are epoxy resins (typically epoxy-novolac systems) with silica fillers, hardeners, catalyst and rubber modifiers used in integrated chip packaging. This process is well illustrated by Figure 6.14. 

Figure 6.14. Transfer moulding of computer-chip packaging systems Figure 1 from (Nguyen, 1993) 1993 IEEE.

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