Binary counter

Here is a model for a parameterized N-bit binary up-down counter with synchronous preset and preclear controls. The counting is synchronized to the rising edge of a clock. 

Here is a model of a modulo-binary up-counter. This counter has only a synchronous preclear control and all transitions occur on the rising clock edge. 

Using JK flip-flops, we can design a circuit that will count a clock signal and provide a divided output of that clock signal. 

This circuit is shown in Fig. 7.1. The circuit is powered by an external %-V source (not shown in the schematic). The clock is mnning at 100 kHz with a 50% duty cycle. The J and pins of the flip-flop are tied high, and the clear and reset pins are tied low. This causes the Q output to change states when the clock goes from low to high. Because 

Copyright 2006 by The McGraw-Hill Companies, Inc. Click here for terms of use. 

The resulting breadboard waveforms are shown in Fig. 7.2. The top waveform is the 100 kHz clock, the middle waveform is the Q output of the first JK flip-flop stage (divide by 2), and the bottom waveform is the Q output of the second JK flip-flop stage (divide by 4). This circuit was simulated using IsSpice, PSpice, and Micro-Cap. The results of each of these simulators are shown in Figs. 7.3, 7.4, and 7.5, respectively. 

For circuits that count to values greater than 4, a counter IC is the more logical choice. Parts such as CD4017 contain any number of these JK counter stages that can be used to count to any number required. 

---

This is a highly recommended method of capacitor switching for installations that are large and require very fine monitoring and correction of p.f. with the smallest number of banks. The entire reactive requirement is arranged in only a few steps yet a small correction up to the smallest capacitor unit is possible. The relay is sequenced so that through its binary counter the required switching is achieved in small steps, with just four or six sets of capacitor units or banks. The operation of the entire sequence can be illustrated as follows ... 

In a typical electronic fuze timer the fundamental components are an oscillator and a binary counter. Lining flueric tech-... 

Figure 7.3 IsSpice waveform results of binary counter circuit.

Figure 7.6 shows the schematic of the complete circuit schematic that provides this logic function. The binary counter circuit (Fig. 7.1) provides the input signals, and the AND gates provide the decoder logic. The clock signal is 100 KHz at 50% duty cycle. 

If the used value of parameter W is odd, then the period of binary counter is maximum and equal to the transformation module. For the first case the step weight value is constant and public, therefore parameter W may be any odd number with a respective width. In that case, an assaulter knows parameter W and can calculate the difference between any pair of counter states St. 

Synthesized netlist of a 2-bit binary counter is // shown in Figure 3-14. 

Figure 3-14 A 2-bit up-down, loadable, clearable binary counter.

A Gray counter is a binary counter with the following conversion logic ... 

In the serial mode, the digital word (number) is sent to the computer one bit at a time. Now a binary counter provides a parallel output since each of the output bits has its own data output channel and the value of each output bit is simultaneously available. To use a serial transmission scheme, this parallel output must be put into serial form. One way to accomplish this is to use a Universal Asynchronous Receiver Transmitter (UART). The detailed operation of the UART will not be given here as it is not germane to the subject of this book. It is sufficient to say that the heart of the UART is a shift register and the shift register is strobed by a signal from the computer that displaces the binary number, bit by bit, sequentially from the register to the computer. 

Storti G., Mazzotti M., Morbidelli M. and Carra S., Robust design of binary counter-current adsorption separation processes, A.l.Ch.E.J. 39 (1993) pp. 471. 

I he basic building block of digital computers is the re >[Sier. a physical device lhal can store a compleie byie or a word. A 16-bil binary counter, for example, can serve as a register that is capable of holding a 16-bil word. 

Figure 23.19. Asynchronous binary counter. From S. P. Perone and D. O. Jones, Digital Computers in Scientific Instrumentation, New York McGraw-Hill, 1973, by permission of the publisher. Copyright 1973 by McGraw-Hill, Inc.

A synchronous binary up-counter is illustrated in Figure 23.21A. Compare this counter with the asynchronous binary up-counter in Figure 23.19. Notice that the synchronous counter requires external gating whereas the asynchronous counter does not this is because the count sequence is generated by the external gates which set up the J and K inputs of each flip-flop. The timing chart in Figure 23.19B for the asynchronous binary counter can also be used for the synchronous counter. 

The sensor cells are addressed using the active matrix addressing technique, using two decoders one that acts as a colnmn driver and the other that acts as a row selector. These two decoders are synchronised using two binary counters one that iterates... 

Figure 10.3 Simulation output of a 3-bit binary counter operating at 20 kHz...

FIGURE 2 A set of seven tiles that implement a binary counter when started with the seed tile S. Strength-2 bonds are indicated by tile sides with two projections (or indentations) other bonds have strength 1. Arrows indicate sites where a tile may be added at 1 = 2. Source Adapted with permission from Winfree, 2000. 

FIGURE 5 Using self-assembly of DNA tiles to create a molecular-scale pattern for a RAM memory with demultiplexed addressing. The tile set is closely related to the binary counter. Source Adapted with permission from Cook et ah, in press. 

We consido here two possible alternatives for control generation, as shown in Figure 8.9. In the first case, binary counters, which are initially cleared, are used to count the number of cycles since the completion of the anchors comparators are then used to determine when the operation should be activated. The offset control in this case corresponds to the binary counter and the synchronization control corresponds to the comparators. For the second case, shift registers are used instead of binary counters. This results in more registers in the offset control but reduces the synchronization control since the need for comparators has been eliminated. 

Scanning circuits are typically made out of a binary counter and a decoder (for example, an LS93 and an LS138) whose output lines successively activate the open collector or trl-state circuits that connect the various decades to the bus, and select the appropriate digit. Some LSI circuits, like the six decade 7301, already Include the scanning circuits. 

The functioning of the counting circuits can be easily checked if they consist of individually accessible decades or binary counters. When one is dealing with LSI counters, where the output lines are time-shared by several decades, the functioning of each decade may be observed by externally triggering a scope with the scanning clock signal. 

---