Synchronous preclear

Here is a model of a modulo-binary up-counter. This counter has only a synchronous preclear control and all transitions occur on the rising clock edge. 

For example, a binary count of 4 bll00 corresponds to a Gray count of 4 bl010. Here is a Verilog HDL model for a parameterized N-bit Gray up-counter with synchronous preclear. 

Here is a model for a parameterized N-bit binary up-down counter with synchronous preset and preclear controls. The counting is synchronized to the rising edge of a clock. 

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