Asynchronous counters

Unlike asynchronous counters, in which the output change of one flip-flop is applied to the clock input and thus changes the state of a succeeding flip-flop, synchronous-counter flip-flop outputs set up the J and K inputs of succeeding flip-flops so that a common clock-signal can cause the proper count sequence to occur. 

A synchronous binary up-counter is illustrated in Figure 23.21A. Compare this counter with the asynchronous binary up-counter in Figure 23.19. Notice that the synchronous counter requires external gating whereas the asynchronous counter does not this is because the count sequence is generated by the external gates which set up the J and K inputs of each flip-flop. The timing chart in Figure 23.19B for the asynchronous binary counter can also be used for the synchronous counter. 

The question arises, why one would use the more complex synchronous counters rather than the simple asynchronous counters One important reason is that in asynchronous counters the various count sequences must ripple from one flip-flop to the next. This means that an incoming count on the first flip-flop, which will... 

Here is an example of an up-down counter with asynchronous preset and clear. 

Having an asynchronous data input such as PresetData can cause a problem. Consider when Preset is 1 and then PresetData changes. The change of PresetData does not reflect in the Verilog HDL model while the change propagates to Counter in the synthesized netlist. Avoid or be careful when using asynchronous data inputs. 

Here is the model for a parameterized N-bit Johnson counter with an asynchronous preclear control. 

In the serial mode, the digital word (number) is sent to the computer one bit at a time. Now a binary counter provides a parallel output since each of the output bits has its own data output channel and the value of each output bit is simultaneously available. To use a serial transmission scheme, this parallel output must be put into serial form. One way to accomplish this is to use a Universal Asynchronous Receiver Transmitter (UART). The detailed operation of the UART will not be given here as it is not germane to the subject of this book. It is sufficient to say that the heart of the UART is a shift register and the shift register is strobed by a signal from the computer that displaces the binary number, bit by bit, sequentially from the register to the computer. 

Often one needs counters in an interface to divide down the clock frequencies and to count such events as the number of data points taken and the number of times data exceed a predetermined threshold. The flip-flop used in modern integrated-circuit counters is the master-slave JK flip-flop. It is used to construct two basic types of counters, asynchronous and synchronous, that will count up or down in a variety of counting schemes. 

Figure 23.19. Asynchronous binary counter. From S. P. Perone and D. O. Jones, Digital Computers in Scientific Instrumentation, New York McGraw-Hill, 1973, by permission of the publisher. Copyright 1973 by McGraw-Hill, Inc.

In addition to an asynchronous binary up-counter, an asynchronous binary down-counter can also be designed. A 4-bit counter will count down from 15 to 0. 

Regarding dissimilar redundancy dissimilarity can be both in hardware and software. Software dissimilarity is achieved by producing two separate software lequirements/solutions and by the use of two separate teams. Increased workload is countered by being able to limit the amount of testing hy virtue of the replication of computation. The two software lines run asynchronously in two processes and their outputs are added or compared to ensure that no demand is made incorrectly. This achieves high integrity hut at the expense of avaUahUity, so that where passivity cannot be tolerated (e.g. fly-by-wire control systems) such architectures must have an alternative central lane in the event of a failure. 

---