Wafer-level underfill

Alternate approaches that eUminate the capillary-flow underfill process currently used by electronics assemblers, involve pushing the problem back to the wafer stage. One process, wafer-level underfill (WLU) (Figure 5.12), consists of applying the underfill material to a bumped wafer and then B-staging the underfill. The wafer is then diced and the die are positioned on corresponding connection pads on an interconnect... 

Properties of nanofillers recently developed nano materials are reported to display greater mechanical strength, greater thermal conductivity and improved electrical performance when compared to materials of normal particle sizes. Nano dimensional materials are being studied as fillers in polymer matrices in a variety of formulations for electrically conductive adhesives, thermally conductive adhesives, encapsulants, printed circuit boards, coatings, catalysts, underfills for flip-chip-attached devices and wafer-level connections. ... 

Li Z, Lee S, Lewis B, Houston P, Baldwin D, Stout E, Tessier T, Evans J. No flow underfill assembly process development for fine pitch flip chip silicon to silicon wafer level integration. Advancing Microelectronics. July/August 2010 20-25. 

This research uses the validated finite-element analyses to study the thermo-mechanical behaviors of the 96.5Sn-3.5Ag, 95.5Sn-3.8Ag-0.7Cu lead-fi ce solders and the classical 63Sn-37Pb solder bumped wafer level chip scale package on PCB assemblies subjected to a novel temperature cycle test. It can be seen that the same scale to the WLCSP and the WLCSP with underfill, the difference of the equivalent total strain range exceed an order of magnitude for all the three solder joints. 

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