Via hole pattern

Exposure characteristics of X-8000K2 and conventional positive photoresist OFPR-800 (Tokyo Ohka Co.) are shown in Figure 1. X-8000K2 shows the comparable sensitivity to conventional one. Line and space and via hole patterns of X-8000K2 are shown in Figure 2. 0.8 jim line and space patterns and 1.2 m via hole patterns were obtained. 

Figure 4. Via-hole pattern formed in PIX film under RIE condition, 2yLim via-hole (X-8000K2 1.2pm thick, PIX 2pm thick).

Figure 11. Tapping Mode AFM image of 35 pm via holes patterned in a photoBCB thin film over a copper substrate before plasma treatment to remove polymer residues ( scum , top) and after plasma treatment (bottom).

Figure 5.36. Scanning thermal microscopy images of 35 fim via holes patterned in a photoBCB thin film over a copper substrate before plasma treatment to remove polymer residues. DC thermal images (left) and AC phase images (right) are shown for frequencies of IkHz (top) and 30kHz (bottom). (From Meyers et al. [174], (2000) American Chemical Society used with permission.) (See color insert.)...

The function of the interlevel dielectric of the multilevel structure is three-fold (1) it must provide planarization of underlying topography while allowing high resolution patterning of via holes necessary for contact between metal layers, (2) it must provide insulation integrity, and (3) it must contribute minimally to device capacitance. 

There are two aspects of tungsten CVD for integrated circuits that have taken on commercial importance. One is the blanket deposition and subsequent patterning, so it can be used as a conductor to replace high-resistivity doped poly. The second area of interest is the "selective" CVD of tungsten, where deposition occurs on silicon but not on silicon dioxide. Here one can selectively fill via holes to either provide a thin barrier metal or to deposit a thicker layer to help planarize the circuit. Both applications involve only one processing step, and are attractive for this reason. 

The plastic film with interconnection layers, denoted (2) in Fig. 16.1, can be made by a process similar to that used to manufacture flexible circuit boards. First, plastic films coated with copper foil are processed by a numerically controlled (NC) drilling machine to make via holes. Plating is then used to make interconnections between top and bottom sides though via holes. Finally, the copper layers are patterned by conventional photolithography and etching. Gold plating is occasionally employed to improve electronic interconnections. 

For many years, nearly all the substrate materials used in the electronics industry were ceramics produced by tape casting (Mistier, 2000). These substrates consist of multiple layers of tape-cast material acting as the insulative carrier, with layers of metal deposited by sputtering, CVD, or evaporation processes. Holes punched into the tapes fill with metal and act as vias or pathways between layers when the tapes are stacked. Stacked layers of tape-cast blanks are laminated together and then sintered to produce a monolithic substrate. This process is detailed in many handbooks on electronics packaging (e g., Harper, 2000). One of the prime benefits is that the layers of the final part can be different different hole patterns, different metallization patterns, even different dimensions on each layer. 

A coiled coil is a protein bundle of 2-5 alpha helices wrapped around each other into a superhelix, also called a supercoil (Lupas, 1996a Mason and Arndt, 2004 Lupas and Gruber, 2005). In the simplest form of coiled coil, helical domains of two proteins wind around one another and bind via a distinctive knobs-into-holes pattern whereby an amino acid side chain of one helix (knob) inserts into a space surrounded by four side chains of the facing helix (hole) as first suggested by Francis Crick in 1952 (Lupas, 1996a Lupas and Gruber, 2005). 

Xia Y, Friend RH. (2007) Nonlithographic patterning through inkjet printing via holes. Appl Phys Lett 90 253513/1-253513/3. 

Patterning of Fine Via Holes in Polyimide by an Oxygen Reactive Ion Etching Method... 

Usually, dry etching of polyimide is performed by RIE with O2, CF, or their mixtures as an etchant gas, utilizing positive photoresist (2), metals such as aluminum (3), spin-on-glass (4), or SiN (5) as an etching mask. However, in the former case, it is difficult to define a fine via-hole as small as 2 pm or less because the resist thickness must be two or more times that of the polyimide as a result of the equal etching rates between photoresist and polyimide. In the latter case, though the fine pattern can be obtained the additional pattern transformation from the photoresist to the masking layer is necessary. 

Figure 2. Resist patterns of X-8000K2 printed by a RA-501 (g line) (a) 0.8jum L S, (b) 1.2pm via-hole.

Inlaid metal patterning schemes were first used in the formation of tungsten studs to fill contact and via holes. In this application, a blanket tungsten film is deposited by CVD thick... 

Wang et al.37 used TaN/Si02/Si substrates with hole pattern, as schematically presented in Fig. 4, for investigating filling via hole by electroless deposition. For this purpose, the ionized cluster beam (ICB) Pd layers with a thickness of 1-2 nm were deposited. The diameter of holes was in the range 0.31-1.0 (dm with depth 1.5 (dm. The solution for electroless deposition of copper and operating conditions, used in Wang s work, is presented in Table 4. 

Specifically for the passivation of temperature sensitive bubble memory devices,these ultrapure materials proved to be of great value. A cure process was optimized to obtain a reliable low temperature cure without affecting the magnetic coercivities of the bubble memory devices. A positive resist process, using a simple development step to pattern via holes in devices has been optimized and successfully used to fabricate devices. The devices fabricated using the the polyimide process have been compared with conventional SiC offers reliable passivations with thinner stress free films for passivations. The fabrications involve simple inexpensive process steps and are compatible with conventional resist processes. The reliability of the imide passivated devices can be considerably enhanced by the use of ultrapure starting materials to preclude harmful ionic mobilities through passivated layers. 

The main contact hole and via etch patterning issues include pattern distortion, proximity, and microloading effects. Figure 13.47 shows cross-sectional SEM images of 110-nm, 160-nm, and 200-nm contact holes patterned into Si02 substrate with an acrylate resist. Note that the resist has been stripped off. The sidewalls of the features are smooth and nearly vertical. 

The next step in part fabrication is the generation of a hole pattern in the tape-cast material. These holes are used to interconnect layers in a multilayered ceramic package or to interconnect the two surfaces of a substrate. The holes are generally circular, but they can be most any other shape. This section will address the techniques and equipment used in the via generation process. 

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