Via hole

Aluminum, the most common material used for contacts, is easy to use, has low resistivity, and reduces surface Si02 to form interfacial metal-oxide bonds that promote adhesion to the substrate. However, as designs reach submicrometer dimensions, aluminum, Al, has been found to be a poor choice for metallization of contacts and via holes. Al has relatively poor step coverage, which is nonuniform layer thickness when deposited over right-angled geometric features. This leads to keyhole void formation when spaces between features are smaller than 0.7 p.m. New collimated sputtering techniques can extend the lower limit of Al use to 0.5-p.m appHcations. 

Deep recesses, holes, and other difficult three-dimensional configurations can usually be coated with relative ease. For instance, integrated circuit via holes with an aspect ratio of 10 1 can be completely filled with CVD tungsten. 

Interconnect. Three-dimensional structures require interconnections between the various levels. This is achieved by small, high aspect-ratio holes that provide electrical contact. These holes include the contact fills which connect the semiconductor silicon area of the device to the first-level metal, and the via holes which connect the first level metal to the second and subsequent metal levels (see Fig. 13.1). The interconnect presents a major fabrication challenge since these high-aspect holes, which may be as small as 0.25 im across, must be completely filled with a diffusion barrier material (such as CVD titanium nitride) and a conductor metal such as CVD tungsten. The ability to fill the interconnects is a major factor in selecting a thin-film deposition process. 

The dependence on film thickness is attributed to the dewetting nucleation, which occurs in the 2.5-4.5 nm thickness range via the formation of randomly distributed droplets rather than the formation of holes. When the initial film thickness exceeds 4.5 nm, dewetting is trigged via nucleation of holes instead of droplets, and for film thickness above 10 nm, dewetting develops slowly via hole nucleation at defects. The different dewetting processes observed for different initial film thicknesses can be explained in terms of the variation of disjoining pressure and the inability of the polymer to spread on its own monolayer. 

The appropriate gas mixture can be supplied to the center of the reactor (4 in Fig. 6) via holes in the lower electrode (2 in Fig. 6). and is pumped out through the space between substrate electrode and the reactor wall to the exhaust (5 in Fig. 6). Alternatively, the gas mixture can be supplied horizontally, parallel to the electrodes, through a flange in the reactor wall, positioned between the electrodes (perpendicular to the plane of the cross section in Fig. 6, not shown). In this case, the gas is pumped out at the opposite side of the supply. 

Driscoll et al. (259,266) concluded that the catalytically active species for OCM are Li -0 centers, which are equilibrated with surface 0 centers via hole transport, because vacant hole sites are formed by Li doping in the surface and bulk. However, direct observation of the Li -0 pairs is difficult, because they are present at high temperatures and are formed only in an O2 atmosphere (267). It has been reported that 0 species in other alkali-doped MgO catalysts are also active for OCM (265,268). 

Electrical conductivity is due to the motion of free charge carriers in the solid. These may be either electrons (in the empty conduction band) or holes (vacancies) in the normally full valence band. In a p type semiconductor, conductivity is mainly via holes, whereas in an n type semiconductor it involves electrons. Mobile electrons are the result of either intrinsic non-stoichiometry or the presence of a dopant in the structure. To promote electrons across the band gap into the conduction band, an energy greater than that of the band gap is needed. Where the band gap is small, thermal excitation is sufficient to achieve this. In the case of most iron oxides with semiconductor properties, electron excitation is achieved by irradiation with visible light of the appropriate wavelength (photoconductivity). 

A double metal process can be used to reduce the cell pitch and minimize parasitic resistance and capacitance, which can be critical for 4H-SiC BJTs intended for high-frequency operations. The finished structure in Figure 6.12(e) can be covered with an intermetallic dielectric layer. Via holes are then opened, and a thick metal... 

The function of the interlevel dielectric of the multilevel structure is three-fold (1) it must provide planarization of underlying topography while allowing high resolution patterning of via holes necessary for contact between metal layers, (2) it must provide insulation integrity, and (3) it must contribute minimally to device capacitance. 

With PSPIs, the photopatterning process involves significantly fewer process steps (Figure 19) and eliminates the need for expensive plasma equipment. However, the process is currently limited to aspect ratios of about 0.5 for negative features such as via holes. Higher aspect ratios can be obtained for positive features such as lines unfortunately, holes are the more-prevalent features for TFML structures. 

Truncated Downcomers/Forward Push Trays Truncated downcomers/forward push trays include the Nye Tray Maxfrac (Fig. 14-26a), Triton , and MVGT . In all these, the downcomer from the tray above terminates about 100 to 150 mm (4 to 6 in) above the tray floor. Liquid from the downcomer issues via holes or slots,... 

Aerosols and mists are formed when liquids are sprayed using compressed gas However this increases the proportion of waste liquid. In order to eliminate waste, a porous diaphragm resembling a cut-off cone is used. Its smaller base borders the face between the nozzle for the liquid and holes for the gas the larger base is connected to the spraying head and forms chambers connected via holes to create a peripheral enclosing air stream. 4... 

An HgCdTe imager chip 130 and Si read-out chips 140 are mounted on a substrate. The imager chip is connected to the read-out chips by an interconnect structure ISO in which a layer 152 of dielectric material is bonded to the chips and has interconnecting conductors disposed thereon and extending through via holes therein into ohmic contact with contact pads of the chips. A flexible portion in the structure enables the read-out and the imager chips to be disposed in different planes to provide a compact structure. 

A different approach to the problem of connecting terminals of individual detectors formed in an HgCdTe layer with corresponding terminals of a read-out device integrated in a semiconductor substrate is to provide connections via holes formed through the thickness of the HgCdTe layer. One particular technique is known as the loophole technique. The characteristic features of this technique are that an HgCdTe substrate is adhered to a... 

In the invention disclosed in JP-A-1061055 a read-out chip is attached to an HgCdTe layer and connection is made via holes through the silicon chip. 

A (100) silicon wafer 10 is anisotropically etched to form hollows 11 having sloped sides 15. A plurality of via holes are etched or laser drilled through the floor 17 of each hollow. Next, the wafer is oxidized to coat its surfaces with a first insulator of SiC>2. A refractory conductor is deposited within the vias to form conductive conduits. A perspective view of a single hollow is shown below. 

There are two aspects of tungsten CVD for integrated circuits that have taken on commercial importance. One is the blanket deposition and subsequent patterning, so it can be used as a conductor to replace high-resistivity doped poly. The second area of interest is the "selective" CVD of tungsten, where deposition occurs on silicon but not on silicon dioxide. Here one can selectively fill via holes to either provide a thin barrier metal or to deposit a thicker layer to help planarize the circuit. Both applications involve only one processing step, and are attractive for this reason. 

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