Resists etching resistance

Incorporation of cyclic aliphatic (aUcycHc) side groups markedly improves the plasma etch resistance of acryhc polymers, without reduciag optical transparency at 193 nm (91). Figure 32 presents stmctures of some acryhc polymers currendy under study for use ia 193-nm CA resists (92—94). Recendy, polymers with main-chain aUcycHc stmctures have been described that offer similar properties (95,96). 

Some nonhygroscopic materials such as metals, glass, and plastics, have the abiUty to capture water molecules within microscopic surface crevices, thus forming an invisible, noncontinuous surface film. The density of the film increases as the relative humidity increases. Thus, relative humidity must be held below the critical point at which metals may etch or at which the electrical resistance of insulating materials is significantly decreased. 

The blanket deposition is then sputter etched through a resist to pattern the metallisation. Selective deposition of W, under development, would deposit metal only in desired areas, and would reduce process steps and costs. 

Etching. After a resist is patterned on a wafer, the exposed or unwanted substrate is removed by etching processes. Subsequentiy the resist is removed, leaving a desired pattern in a functional layer of the integrated circuit. Etching is performed to pattern a number of materials in the IC fabrication process, including blanket polysiHcon, metal layers, and oxide and nitride layers. The etch process for each material is different, and adapted to the material requirements of the substrate. 

Step 2. A resist is deposited on the Si N and patter (mask 1). AH Si N and Si02 not covered by the resist (the resist covers the final transistor area) is etched away. 

Step 7. K blanket layer of polysiUcon and pattern (mask 2), such that the resist covers only the polysiUcon that is to become the gate, is deposited. All exposed polysiUcon is etched away. 

Step 9. Si02 is blanket deposited over the substrate. The resist (mask 3) that has openings over the Si02 is deposited and patterned. The exposed Si02 is etched down to the source, drain, and gate layers, creating contact windows for metallisation. 

Step 10. The system is metallised, first with a tungsten layer, then with Al. The resist is appHed and patterned (mask 4), and unwanted metal is etched away. 

Step 11. If no additional metallisa tion layers are required, the substrate is covered with a passivation layer. If additional levels of metallisa tion are to be added to the stmcture, a blanket layer of a intermetal dielectric (IMD) is deposited. The resist is deposited, patterned (mask 5), and vias down to the Al in the first metal layer are etched. Steps 10 and 11 are repeated to form the second metal layer. 

Fig. 9. Fabrication sequence for an oxide-isolated -weU CMOS process, where is boron and X is arsenic. See text, (a) Formation of blanket pod oxide and Si N layer resist patterning (mask 1) ion implantation of channel stoppers (chanstop) (steps 1—3). (b) Growth of isolation field oxide removal of resist, Si N, and pod oxide growth of thin (<200 nm) Si02 gate oxide layer (steps 4—6). (c) Deposition and patterning of polysihcon gate formation of -source and drain (steps 7,8). (d) Deposition of thick Si02 blanket layer etch to form contact windows down to source, drain, and gate (step 9). (e) Metallisation of contact windows with W blanket deposition of Al patterning of metal (steps 10,11). The deposition of intermetal dielectric or final...

These processes are considerably more complex in actual CMOS fabrication. First, the lower layers of a CMOS stmcture typically have a twin-tub design which includes both PMOS and NMOS devices adjacent to each other (see Fig. 3b). After step 1, a mask is opened such that a wide area is implanted to form the -weU, followed by a similar procedure to create the -weU. Isolation between active areas is commonly provided by local oxidation of sihcon (LOCOS), which creates a thick field oxide. A narrow strip of lightly doped drain (LDD) is formed under the edges of the gate to prevent hot-carrier induced instabiUties. Passivation sidewalls are used as etch resists. A complete sequence of fabrication from wafer to packaged unit is shown in Figure 10. 

Cadmium usage, illegal in most of Europe, is being discouraged elsewhere. The U.S. military has cadmium specifications for electronic, fastener, and marine equipment, which requires only cadmium. Tin is being substituted for tin—lead as a metallic etch resist during printed circuit board production. 

Copper is universally used as the metal plating for tape because it can be easily laminated with copper and the various plastic tapes. Copper is readily etched and has excellent electrical and thermal conductivity in both electrodeposited and roUed-annealed form. The tape metal plating is normally gold- or tin-plated to ensure good bondabiUty during inner- and outer-lead bonding operations and to provide better shelf life and corrosion resistance. 

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