Wiring delay

Sakurai T (1983) Approximation of wiring delay in MOSFET LSI. IEEE J Solid-State Circuit 18 418-426... 

Lumped Capacitance of inter-chip contact (fF) Bus Wire Delay (ns) Critical Path Delay (ns) Clock Frequency (MHz) Improvement to 2D Solution... 

C. Kim, D. Burger, S. W. Keckler. Nonuniform cache architectures for wire-delay dominated on-chip caches. IEEE Micro, Vol. 23, Nov.-Dec. 2003, pp. 99 - 107. 

We show that a linear-wire-delay model is sufficient to model the impact of buffering for the latch placement problem. 

Theoretical results published by Otten [17] and discussed in Sect. 3.3 indicate that optimal buffer insertion on a two-pin net results in a wire delay that is linearly-proportional to its length. The RUMBLE model heavily relies on these results. 

In practice, it is difficult to evaluate the exact effect of high-level transformations. At this point in the synthesis process, measures such as size, power, and delay are only estimates, as they can be evaluated exactly only when the real hardware is generated. For example, what may seem to be a critical path with respect to timing may turn out to be faster than other paths after logic synthesis. In contrast, a path that appears to be fast at a high level may turn out to be critical l cause of unexpected wire delays. Thus, high-level transformations must be applied with care, and often only the designer can decide which transformations to apply. 

The individual clusters are then placed using a min-cut placement algorithm, and wiring, delays, chip area, clock period, and the average cycle time are estimated. 

For the design, a problem-oriented and abstract high-level design methodology and design description language should be used. There should be adequate testability (for production test). Gate and interconnection (wire) delays should be considered. 

This model includes transport wire delays and pin-to-pin delays on a zero delay functional network. Timing constraint violations are reported as warning messages. 

This delay model is used for detailed timing verification. Transport wire delays and pin-to-pin delays are included in this delay model. 

These models include transport wire delays and pin-to-pin delays in the delay model. In addition to warning messages, the Simulator can schedule X output values for timing constraint violations and circuit hazards. One can use the FTGS library for fast, sign-off-quality timing verification. 

As more is learned about the detailed needs of designers for tool capability and interaction, tools must be augmented or modified to support these needs. Two such changes that have already been identified are more accurate wire delay modeling so as to be able to model delays on ICs and PC boards and between cabinets, and more accurate delay modeling of circuits containing multiplexers. 

For comparison purposes, we linearly scaled down each functional unit area and delay from 3-micron process parameters. We used different device parameters for different fabrication processes to calculate wiring delay in this program. Our experiments shows interconnection delay time contributes 20% of functional unit delay to overall delay with 1.6 micron fabrication process. The overall delay time could be reduced to 5% above functional delay by introducing redundant operators along the critical path. 

Pravil Gupta. PLA and Wire Delay Analysis. Internal Report, in progress. 

Finally, a timing simulation needs to be performed when the technology net-list has been placed and routed and the timing information is back-annotated to the design to include wiring delays. 

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