Interconnects fabrication

Pt—Q—Salt, [Pt(NH3)2(HP04)] and [Pt(OH)3] (259,260). Chloride-based baths have been superseded by P-Salt-based baths, which are more stable and relatively easily prepared. Q-Salt baths offer even greater stabiUty and produce hard, bright films of low porosity. Plating under alkaline conditions employs salts of [Pt(OH3)] . These baths are easily regenerated but have low stabiUty. Platinum films have uses in the electronics industry for circuit repair, mask repair, platinum siUcide production, and interconnection fabrication (94). Vapor deposition of volatile platinum compounds such as [Pt(hfacac)2] and... 

A current example of a problem that can be simplified through segregation of its components by physical scale is the deposition of on-chip interconnects onto a wafer. Takahashi and Gross have analyzed the scaling properties of interconnect fabrication problems and identified the relevant control parameters for the different levels of pattern scale [135], They define several dimensionless groups which determine the type of problem that must be solved at each level. 

One of the challenges in interconnection fabrication on a chip is the electrodeposition of Cu in vias of small diameter (<0.2/rm). Modeling of these processes shows that new Cu electrodeposition solutions and new deposition techniques are necessary to solve the problems introduced by the development of new integrated circuits (22). 

A metal interconnect fabrication process is disclosed in US-A-5384267. A metal layer and a photoresist layer are formed on an array of HgCdTe detectors. The photoresist layer is patterned to form a positive mask and the metal interconnect is formed by using a dry etching technique. 

Licata TJ, Colgan EG, Harper JME, Luce SE. Interconnect fabrication processes and development of low-cost wiring for CMOS products. IBM J Res Develop 1995 39 419-435. 

FIGURE 15.6 Cross-sectional view of interwafer interconnects fabricated by Patti et al. Modified from Ref 40. 

Electroless Process for ULSI Interconnects Fabrication Process... 

Electroless deposition processes have distinct advantages, as shown in the first section for ULSI fabrication process. We have proposed one candidate for the electroless process, and we have found Ni-alloy films show superior properties for the capping and barrier layer. Moreover, we introduce our new process called the all-electroless process for ULSI interconnect fabrication. 

Keywords 3-dimensional VLSI, 2.5-D integration, inter-chip contact, interconnection, fabrication, test, design technology. 

The result is the formation of a dense and uniform metal oxide layer in which the deposition rate is controlled by the diffusion rate of ionic species and the concentration of electronic charge carriers. This procedure is used to fabricate the thin layer of soHd electrolyte (yttria-stabilized 2irconia) and the interconnection (Mg-doped lanthanum chromite). 

Metallization. Integrated circuits require conductive layers to form electrical connections between contacts on a device, between devices on a chip, between metal layers on a chip, and between chips and higher levels of interconnections needed for packaging the chips. It is critical to the success of IC fabrication that the metallization be stable throughout the process sequence in order to maintain the correct physical and electrical properties of the circuit. It must also be possible to pattern the blanket deposition. 

Interconnect. Three-dimensional structures require interconnections between the various levels. This is achieved by small, high aspect-ratio holes that provide electrical contact. These holes include the contact fills which connect the semiconductor silicon area of the device to the first-level metal, and the via holes which connect the first level metal to the second and subsequent metal levels (see Fig. 13.1). The interconnect presents a major fabrication challenge since these high-aspect holes, which may be as small as 0.25 im across, must be completely filled with a diffusion barrier material (such as CVD titanium nitride) and a conductor metal such as CVD tungsten. The ability to fill the interconnects is a major factor in selecting a thin-film deposition process. 

The rapid fabrication of covalently bonded ID functional molecular lines with predefined location, direction, and length provides a means to make a predesigned interconnection of molecular lines running along and across the dimer rows. Indeed, the perpendicularly connected allyl mercaptan and styrene lines or allyl mercaptan and acetone lines have been fabricated on the H-Si(l 00)-2 X 1 surface. °° 2 ... 

Ceramic boards are currently widely used in high-performance electronic modules as interconnection substrates. They are processed from conventional ceramic precursors and refractory metal precursors and are subsequently fired to the final shape. This is largely an art a much better fundamental understanding of the materials and chemical processes will be required if low-cost, high-yield production is to be realized (see Chapter 5). A good example of ceramic interconnection boards are the multilayer ceramic (MLC) stractures used in large IBM computers (Figure 4.11). These boards measure up to 100 cm in area and contain up to 33 layers. They can interconnect as many as 133 chips. Their fabrication involves hundreds of complex chemical processes that must be precisely controlled. 

FIGURE 4.15 Cross-section of multilevel interconnections for advanced bipolar devices. Fourteen separate layers are laid down in the fabrication of interconnections such as the one shown. The precise orientation and composition of these layers are controlled by chemical process steps. Copyright 1982 by the International Business Machines Corporation. Reprinted with permission. 

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