Gate silicon oxide

Conventional electronic devices are made on silicon wafers. The fabrication of a silicon MISFET starts with the diffusion (or implantation) of the source and drain, followed by the growing of the insulating layer, usually thermally grown silicon oxide, and ends with the deposition of the metal electrodes. In TFTs, the semiconductor is not a bulk material, but a thin film, so that the device presents an inverted architecture. It is built on an appropriate substrate and the deposition of the semiconductor constitutes the last step of the process. TFT structures can be divided into two families (Fig. 14-12). In coplanar devices, all layers are on the same side of the semiconductor. Conversely, in staggered structures gate and source-drain stand on opposing sides of the semiconductor layer. 

The electrical current flows from the source, via the channel, to the drain. However, the channel resistance depends on the electric field perpendicular to the direction of the current and the potential difference over the gate oxide. Should this surface be in contact with an aqueous solution, any interactions between the silicon oxide gate and ions in solution will affect the gate potential. Therefore, the source-drain current is influenced by the potential at the Si02/aqueous solution interface. This results in a change in electron density within the inversion layer and a measurable change in the drain current. This means we have an ion-selective FET (an ISFET), since the drain current can be related to ion concentration. Usually these are operated in feedback mode, so that the drain current is kept constant and the change of potential compared to a reference electrode is measured. 

Here, 41 indicates the thin film transistors, 51 the substrate, 43 a dielectric layer, 49 polysilicon gates, 50 gate electrodes, 55 contact plugs, 56 bottom electrodes, 53 the planarization layer, 54 the mercury cadmium telluride layer and 57 the top electrode layer. The planarization layer is formed from silicon oxide, silicon nitride, silicon oxide nitride or from a polyimide. The planarization layer may be formed as a double or triple layer. 

Bottom-gate, top-contact (Fig. 4.2a) and a bottom-gate, bottom-contact (Fig. 4.2b) TFT configurations are used to evaluate the FET performance of our semiconductors. The devices are built on an n-doped silicon wafer (gate electrode) with a 100-nm thermal silicon oxide (SiC>2) dielectric layer which is modified with a self-assembled monolayer of octyltrichlorosilane (OTS-8) to promote molecular ordering in the semiconductor layer. For the top-contact device the semiconductor layer ( 20-50 nm) is deposited on the OTS-8-modified SiC>2 surface by spin coating. A... 

Fig. 12 An electronic device based on a single rolled-up sheet of carbon atoms. (From Ref. () In the figure, a CNT (red about 1 nm in diameter) bridges two closely spaced (400 nm apart) platinum electrodes (labeled source and drain) atop a silicon surface coated with an insulating silicon oxide layer. Applying an electric field to the silicon (via a gate electrode, not shown) turns on and off the fiow of current across the nanotube, by controlling the movement of charge carriers onto the nanotube. (View this art in color at www.dekker.com.)...

Pentacene is attracting considerable attention as its charge transport properties are excellent [4, 48], and films of pentacene on silicon oxide are commonly used for thin film transistors in which the silicon oxide serves as gate dielectric. 

The most simple pentaeene OTFT test structure used in many labs is based on a Si wafer piece covered with a thermal oxide. Here, the heavily doped Si wafer takes the role of the back gate electrode, and the Si02 takes the role of the gate dielectric. A pentacene thin film is deposited as the semiconducting layer. Source and drain electrodes are deposited either on the silicon oxide (bottom contact) or on top of the pentacene film (top contact). 

To test the electrical stability of the Cu-Zn alloy and Cu on silicon oxide, a 50nm gate oxide with an A1 back contact on p-substrate was prepared. By sputtering through a shadow mask, metal oxide semiconductor (MOS) dots of 1.2mm diameter were developed. The specimens were annealed at different temperatures and tested for bias temperature stability. 

Surface treatment has also been used to modify the threshold voltage as well as measured mobility in pentacene and Cgo TFTs [60]. These transistors have a heavily doped silicon/silicon oxide gate dielectric structure where alkyl, aUcylamine, and fluoroalkyl silanes are used to modify the Si02. Evaporated pentacene and Cgo form the active p- and n-type semiconductors. The experimental effect of these monolayer treatments is to alter Vj and effective mobility dramatically (see Table 3.2.3). For pentacene, the mobility decreases from -F, -CH3, untreated, -NH2, with a similar shift in Vj from 17 to -11V. The opposite trend is observed for Cgo, in which mobility is largest for the untreated material and smallest for the fluorinated SAM. In the case of Vji the alkylamine SAM shows the lowest VjOi 5.3 V. The underlying reasons for these trends are not completely understood. What is intriguing is how dramatic... 

Graphene field-effect transistors with a parylene back gate and an exposed graphene top surface have been reported [40]. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted an optical reflection microscopy technique to be used for the identification of exfoliated graphene flakes. At room... 

Semiconductor processing technologies have often been used to produce ISEs, particularly as field-effect transistors (FETs) with ion-selective layers like silicon oxide over the gate region. Such ion-selective FETs (ISFETs) are, in principle, solid ISEs, although sometimes the dielectric over the gate is covered with a second, liquid membrane-type layer to achieve different selectivities. 

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