Dielectric passivation layers

Avatrel Dielectric Polymers (low-k dielectric applications such as interlayer dielectrics, passivation layers, die attach adhesives, chip encapsulants (both molding and adhesive) and underfill materials). 

Step 11. If no additional metallisa tion layers are required, the substrate is covered with a passivation layer. If additional levels of metallisa tion are to be added to the stmcture, a blanket layer of a intermetal dielectric (IMD) is deposited. The resist is deposited, patterned (mask 5), and vias down to the Al in the first metal layer are etched. Steps 10 and 11 are repeated to form the second metal layer. 

Polyimides, both photodefinable and nonphotodefinable, are coming iato iacreased use. AppHcatioas iaclude planarizing iatedayer dielectrics oa iategrated circuits and for interconnects, passivation layers, thermal and mechanical stress buffers ia packagiag, alpha particle barriers oa memory devices, and ion implantation (qv) and dry etching masks. 

Passivation layers, multilayer resist stacks, diffusion barriers, interlevel dielectrics, side-wall spacers, trench masks, oxidation masks, etc., in semiconductor devices. 

Passivation layers, surface dielectric, and doping barriers in semiconductor devices. 

The passivation of silicon, motivated by the centrality of this semiconductor to the microelectronics industry, has been well studied. In addition to excellent passivation allowed by the silicon oxide, silicon can also be passivated with silicon nitride (Si3N4), other dielectrics, metal layers, and hydrogen. Here we focus only on hydride termination, since in addition to acting as a passivating layer for the underlying silicon, the hydride groups provide a versatile starting point for subsequent attachment chemistry. 

Finally, we will consider PECVD silicon oxynitrides, and their unique characteristics. When oxygen is added to a PECVD nitride film, there are indications that it may improve its crack resistance as a final passivation layer.13 Also, there may be advantages in terms of its electrical characteristics as an interlayer dielectric. Therefore, the nature of films grown when N20 is added to a SiH4, NH3 and He gas mixture in a high frequency (13.56 MHz), cold-wall, parallel-plate reactor have been studied. 

Although the surface of most IC chips has been passivated with a layer of inorganic dielectric material such as silicon dioxide or silicon nitride (polyimides have also been used as final passivating layers), the protection provided by such layers is not sufficient to ensure reliable operation throughout the lifetime of the device. The three basic methods of protection are... 

Gate Dielectrics and Surface Passivation Layers for Organic Field Effect Transistors... 

Silicon nitride (Si3N4) is commonly used in silicon microelectronics and micromechanics as a passivation layer and, because of its dielectric properties, it is also widely used in capacitors. The dielectric constant of silicon nitride is twice as high as the dielectric constant of silicon oxide, thus allowing higher capacitances for identical capacitor geometries. 

Silicon nitride as a passivation layer on top of an electronic circuit or a metal structure is an excellent diffusion barrier against water and protects the electronic device from organic and metallic (e.g., Na, K) contaminants. Silicon nitride is also used as a masking layer for wet anisotropic etching of silicon (in KOH), as part of a dielectric membrane, and for mechanical protection in micromechanics during face-down handling of the front of electronics while processing the back of the wafer, a silicon nitride passivation layer prevents defects and scratches on the sensitive front side. 

FIGURE 6.3.15 (a) The cross-sectional illustration of organic transistors on plastic films with polyimide gate dielectric layers and parylene passivation layers. Transfer characteristics with bending radii of = 20, 10, 5, 2, 1, and 0.5 mm these correspond to inward (b) and outward (c) bending strains. A Vq is swept from 20 to -40 V with application of = 0 V. 

Fig. 4.13. The process flow presented in [74]. Each layer is patterned using a shadow mask, except for the surface passivation layer which is blanket deposited. The surface passivation layer does not introduce any significant resistance between the gate and source/drain layer. The gate dielectric layer is only deposited where necessary due to the nature of the shadow mask geometry.

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