Dielectric layer fabrication

New process technology development must be carried out to achieve higher frequency modules and higher levels of integration. The processes for forming wiring conductors and the processes for dielectric layer fabrication are described separately below. 

However, fluorocarbon compounds might be of considerable interest for LB-layer fabrication. Their dielectric and mechanical characteristics and thermal and chemical stability are not inferior to those of polyimides, and highly developed synthesis technology makes it possible to create systems with various predictable properties. Such films have been found to demonstrate a high degree of perfection and excellent dielectric characteristics.69,70... 

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

The electrochemical etch-stop technology that produces the silicon island is rather complex, so that an etch stop directly on the dielectric layer would simplify the sensor fabrication (Sect. 4.1.2). The second device as presented in Fig. 4.6 was derived from the circular microhotplate design and features the same layout parameters of heaters and electrodes. It does, however, not feature any sihcon island. Due to the missing heat spreader, significant temperature gradients across the heated area are to be expected. Therefore, an array of temperature sensors was integrated on the hotplate to assess the temperature distribution. The temperature sensors (nominal resistance of 1 kfl) were placed in characteristic locations on the microhotplate, which were numbered Ti to T4. 

Instead of a silicon island underneath the dielectric layer, a polysilicon plate can be placed in the membrane center. Such a device was not fabricated, but the effect of a heat spreader that is integrated in the dielectric membrane was demonstrated by simulations. The results of the simulations are discussed in Sect. 4.2.2 [115,116]. 

Another possibihty to improve the temperature homogeneity is to introduce an additional polysiHcon plate in the membrane center. The thermal conductivity of polysilicon is lower than that of crystalline siHcon but much higher than the thermal conductivity of the dielectric layers, so that the heat conduction across the heated area is increased. Such an additional plate constitutes a heat spreader that can be realized without the use of an electrochemical etch stop technique. Although this device was not fabricated, simulations were performed in order to quantify the possible improvement of the temperature homogeneity. The simulation results of such a microhotplate are plotted in Fig. 4.9. The abbreviations Si to S4 denote the simulated temperatures at the characteristic locations of the temperature sensors. At the location T2, the simulated relative temperature difference is 5%, which corresponds to a temperature gradient of 0.15 °C/pm at 300 °C. 

Fig. 11 (a) Schematic of an a-substituted quinquethiophene liquid crystalline monolayer assembled on an SU8 organic gate dielectric layer of an FET. (b) Transfer characteristics in the linear and saturation regimes for a 20 pm channel length monolayer FET fabricated (inset) in a ring geometry... 

The type of adhesion dealt with in the examples in the second paragraph above and Fig. 1 is mechanical or structural while for the lithographic resist adhesion requirements described in this paper a more practical definition of adhesion, one first proposed by Mittal [16], is being referenced and used. Resist patterning layer-substrate adhesion is required only to process or pattern a particular device layer. After the circuit layer is patterned, the resist layer is removed and does not become an integral part of the circuit, as opposed to a PI interlevel metal dielectric layer which does. As such, it is not required to possess high mechanical adhesion strength. In fact, the resist layer must be quantitatively removed after the circuit required layer has been patterned. If the resist layer adheres too well and becomes difficult to remove, it actually interferes with successful circuit fabrication. 

Unique Process Requirements. The fabrication of TFML interconnections involves a repetitive sequence of thin-film processes to deposit and pattern conductor and dielectric layers. Many processes used in IC fabrication, such as vacuum deposition of metals, photolithography, wet and dry etching, and newly emerging processes (such as laser etching and deposition), may be used in the fabrication of TFML interconnections. However, the geometries and substrates required for packaging impose a number of unique requirements on conventional thin-film processes. 

Hollow planar waveguides have been fabricated by several techniques, including physical vapor deposition and CVD of silver and dielectric layers on metallic substrates. Nevertheless, better results can be obtained by taking advantage of silicon micromachining techniques. Perhaps the most important advantage of silicon hollow waveguides over other hollow structures is the... 

TFML interconnections are fabricated using a repetitional sequence of thin film processes to deposit and pattern the conductor and dielectric layers. A variety of individual processes and process sequences, including both additive and subtractive approaches, have been used. The subtractive process sequence shown in Figure 2 has been used at Honeywell for a variety of patterns (8 ) and is offered as an example. 

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