Collector-emitter voltage

If the switch is a BJT, this is a clear no-no because a bipolar attempts to block reverse voltage, but is really not designed to operate with any reverse collector-emitter voltage. 

For a BJT, the Bias Point Detail gives the collector current, the collector-emitter voltage, and some small-signal parameters for the BJT at the bias point. For a jFET, the Bias Point Detail gives the drain current, the drain-source voltage, and some small-signal model parameters at the bias point. The results of the Bias Point Detail are contained in the output file. We will illustrate the Bias Point Detail analysis with the circuit below ... 

In this section we will investigate how the DC current gain (Hfe) of a bipolar junction transistor varies with DC bias collector current Icq, DC bias collector-emitter voltage Vceq, and temperature. We will use the basic circuit shown below for all simulations ... 

The next thing we would like to do is to see how the Hfe versus Ic curve is affected for different values of DC collector-emitter voltage. The curve in the previous example was generated at VCe = 5 V. We would now like to generate four curves at different values of Vce and plot them all on the same graph. We will generate curves at Vce = 2 V, 5 V, 10 V, and 15 V. We will use the same circuit and simulation profile as in the previous section ... 

Note that the Output variable is VCE(Ql), the collector-emitter voltage of Ql. MIN and LOW are selected, so we are asking for the minimum value of Vqj. Run the analysis. The results are given at the end of the output file ... 

One problem, or should we say challenge, in designing this type of circuit is to ensure that the Darlington pair transistors are not overstressed by causing them to dissipate too much power. The maximum power the transistor can dissipate decreases with increasing collector-emitter voltage. 

An enhancement to the efficiency of the Class B amplifier makes use of the addition of a third harmonic component of the right amount to the collector-emitter voltage waveform to cause near square-wave flattening when it is near zero (where the collector current is greatest). This modification alters the amplifier enough so that it enjoys a different classification called Class F. Flattening enhances efficiency by as much as one-eighth so that... 

It is not convenient to analyze the Class C amplifier by means of the loadline argument as in the cases of Classes A or B, but rather, a time- or phase-domain analysis proves to be more workable. The reason is that in the other classes conduction time is fixed at full time or half In Class C, the conduction time is variable so that a general analysis must be performed where time or phase is the independent variable, not collector-emitter voltage. A time or phase analysis for Classes A or B could have been done, but then only one method would be presented here and the intention is to present another way. The results are the same and comparisons presented at the end of this section. 

A phase domain diagram of the nonsaturated Class C amplifier is shown in Fig. 7.55 along with a representative schematic diagram. The term nonsaturated means that the active device is not driven to the point where the collector-emitter voltage is at the lowest possible value. The curve of V 0) in Fig. 7.55(a) does not quite touch the zero line. Another way of saying this is that the transistor is always active or never conducts like a switch. It is active in the same way as Classes A and B, and because of this similarity, it may be modeled in the same way, that is, as a dependent current source. 

The collector-emitter voltage VceiO), is sinusoidal, but it radians out of phase with the collector current. 

The collector-emitter voltage V ( ) swings from 2 Vcc to zero and differs from the voltage across the load R by the DC component Vcc- Stated before, /acH( ) harmonic currents, do not enter the equations because these currents do not appear in the load. 

Figure 7.59(a) illustrates the collector current vs. collector-emitter voltage behavior of the saturated transistor. Of course, the saturation angle is always contained within the conduction angle. The circuit diagram in Fig. 7.59(b) is the same as Fig. (7.55 b). 

The transistor collector current and collector-emitter voltage waveforms are sinusoidal, which they... 

The onset of saturation occurs when the collector-emitter voltage equals the saturation voltage. Ron is finite allowing Vsat to be greater than zero so that the saturated collector current is finite during saturation. 

The nonlinear characteristic between the collector and emitter cannot be expressed by any conventional nonlinear resistor model, such as the TYPE-92 resistor, because its characteristic depends not only on its terminal voltage Vce but also on the base current Jg. The resistor is expressed by the TYPE-91 TACS-controlled resistor. Its resistance is calculated in the TAGS according to the collector-emitter voltage CE> base current and transient characteristic of a transistor. This modeling technique is explained in Section 4.2.3. 

---