Flip-flop clocked

A more versatile flip-flop than the RS type is called a clocked flip-flop (Fig. 23.13), which can be used for counting operations. The clocked flip-flop has direct set Su and direct clear Cj, inputs that operate in the same manner as the S and C inputs of the RS flip-flop. (This is commonly called asynchronous operation, since no timing requirements are made.) For asynchronous operation, the same truth table as presented in Table 23.4 can be used, by substituting and for S and C. The clocked flip-flop has, however, another mode of operation called the synchronous mode. In the synchronous mode, information is entered into the flip-flop through... 

Figure 23.13. The clocked flip-flop. From S. P. Perone and D. O. Jones, Digital Computers in Scientific Instrumentation, New York McGraw-Hill, 1973, by permission of the publisher. Copyright 1973 by McGraw-Hill, Inc. 

Table 23.5. Clocked Flip-Flop Truth Table...

Normally, one would not have to connect a clocked flip-flop into the JK mode since many integrated-circuit JK flip-flops are available (see Fig. 23.15). Notice that the gated S and C inputs are renamed J and K. The connections from J and K to Q and Q are made internally and usually do not appear on the diagram. 

A master-slave flip-flop is actually two flip-flops in one, with a master flip-flop that feeds data to a slave flip-flop. A JK master-slave flip-flop and clock-input waveform are presented in Figure 23.16. In this figure, the various internal gates and connections are presented for the sake of illustration. In actual practice, the symbols for master-slave flip-flops are not distinguished from those already presented almost all clocked flip-flops available in integrated-circuit form are of the master-... 

A data latch can be built using JK flip-flops, clocked flip-flops, and all varieties of synchronous master-slave flip-flops (see Figure 23.17B). The clocked flip-flop data-latch operates in much the same way as the RS flip-flop data-latch the TP line must undergo a negative-going 1 to 0 transition each time data is transferred. However, the clocked flip-flop data-latch will operate only in a synchronous manner (that is, each time a negative-going clock pulse is present), in contrast to the RS flip-flop data-latch, in which the outputs will follow the inputs whenever the TP input is 0. 

The simplest shift-register is the serial I/O type, shown in Figure 23.18 (omitting the dashed-line outputs). The 4-bit register presented is constructed from master-slave clocked flip-flops. (It can also be constructed from JK flip-flops in exactly the same manner but it cannot be constructed from RS flip-flops.) Notice that a shorthand notation, with the AND gate symbols omitted, is used for the clocked flip-flops. 

Simple digital systems are assembled from well-known libraries of parts combinational logic gates (and, or, inverters, tri-state buffers) storage elements (flip-flops, registers, RAM) synchronization parts (clocks, dividers). From these parts are assembled a huge variety of systems, but all of them can be understood in terms of these basic parts. 

The first circuit we will look at is an op-amp circuit that drives the clock of a J-K flip-flop. Wire the circuit shown below ... 

S0UIT1DI1 Wire the circuit as shown. A 1 kHz clock is used. Use the capacitor startup circuit on page 495 to preset the first flip-flop to 1 and the remaining flip-flops to 0. Note that the initial condition of the capacitor is set to zero. 

Using JK flip-flops, we can design a circuit that will count a clock signal and provide a divided output of that clock signal. 

This circuit is shown in Fig. 7.1. The circuit is powered by an external %-V source (not shown in the schematic). The clock is mnning at 100 kHz with a 50% duty cycle. The J and pins of the flip-flop are tied high, and the clear and reset pins are tied low. This causes the Q output to change states when the clock goes from low to high. Because... 

The resulting breadboard waveforms are shown in Fig. 7.2. The top waveform is the 100 kHz clock, the middle waveform is the Q output of the first JK flip-flop stage (divide by 2), and the bottom waveform is the Q output of the second JK flip-flop stage (divide by 4). This circuit was simulated using IsSpice, PSpice, and Micro-Cap. The results of each of these simulators are shown in Figs. 7.3, 7.4, and 7.5, respectively. 

The assignment to output Zee occurs only at the falling edge of the clock. Variable Zee is inferred to be a falling-edge-triggered flip-flop. The flip-flop shown in the figure has a data-select, that is, the input Control selects either A or B as the data for the flip-flop. 

The variable Counter is assigned under the control of a falling edge of clock ClockB. Thus, two falling-edge-triggered flip-flops are synthesized for Counter. 

Hip-flop inference rule is simple If a variable is assigned a value under the control of a clock edge, a flip-flop is generated an exception to this rule is when a variable is assigned and used only locally within an always statement as an intermediate variable. 

Figure 2-48 Flip-flops inferred from a variable assigned under clock control.

If a falling-edge-triggered flip-flop are to be inferred, then the clock edge event posedge Clk needs to be replaced by ... 

Integer variables assigned under the control of a clock edge are also inferred as flip-flops. Here is an example where an integer variable is assigned under clock control. Four flip-flops are inferred for the variable IntState) the other high-order bits of the variable are optimized away (since they are not used). 

In all the above cases, a variable was assigned under the control of a clock and its value was used outside of the always statement, thus requiring its value to be saved in a flip-flop. 

What happens in the above case if we switch the order of the statements around In this case, since the value of Temp is used before its assignment, its value needs to be retained across multiple clock cycles, thereby inferring flip-flops for Temp. Temp models the internal state of the always statement. This is shown in the following example, where Temp is used before its assignment. 

No flip-flops are inferred for Temp since it is locally declared within the always statement and a value is assigned to the variable and used immediately in the same clock edge. Flip-flops are inferred for NextState (as this... 

The synthesized netlist is the same as in Figure 2-48. Notice that on every clock edge, NextState always get the value of Temp assigned in the previous clock cycle, but not so in the synthesized netlist. The recommendation here is to avoid using locally declared variables in this fashion. Hopefully a synthesis tool will issue a warning if no flip-flops are inferred for Temp. 

Since NextState is assigned a value under the control of a clock edge (Stmt C) and it is also assigned asynchronously (Stmt A and B), a falling-edge-triggered flip-flop with asynchronous preset and clear is synthesized. This is shown in Figure 2-53. Note that four flip-flops are required. The first flip-flop (the leftmost bit of NextState) has both asynchronous preset and clear terminals since it needs to be preset on Reset and cleared on Set. Similarly, the fourth flip-flop has both asynchronous preset and clear terminals since it needs to be preset on Set and cleared on Reset. The... 

What if we want to model a flip-flop with synchronous preset and clear In such a case, simply describe the synchronous preset and clear logic within a clocked always statement (an always statement with a clock event). Here is an example. 

A task call can represent either combinational logic or sequential logic depending on the context under which the task call occurs. By this, we mean that the output parameters of a task call may imply memory depending on the context in which they are assigned. For example, if a task call occurs in a clocked always statement (always statement with a clock event), then an output parameter in a task call may be synthesized as a flip-flop this is determined by using the flip-flop inference rales. A synthesis system implements a task call by expanding the task call in-line with the rest of the code in effect, no separate hierarchy for the task call is maintained. 

In this example, variable ByteOut is assigned a value under the control of clock ClockFa thus, ByteOut gets synthesized as a flip-flop. The code after in-line expansion of the task call looks like this. 

If a variable is assigned a value z in an always statement in which the variable is also inferred as a flip-flop, then it becomes necessary to save the enabling logic of the three-state also in a flip-flop. Here is the same example as above except that the always statement is controlled by a clock event. 

Synthesis infers four flip-flops for this model, three for variable Previous and one for SeqFound. However, optimization reveals that one of the flip-flops for Previous is not necessary and hence it is removed. In this model, the output is latched since it is assigned a value under the control of a clock edge. If a latched output is not desired, then the assignment to SeqFound must be done outside the always statement. Such a module is shown next. 

Here is the behavioral model for the transmitter block TX. This model is a synthesizable model. Rising-edge-triggered flip-flops are inferred for variables TBR, TR, TRE, TBRE, DOUT, CBTT and PA this is because these variables are assigned values under the control of clock CK. 

Here is a synthesizable model for the divider block DIV. This circuit produces a pulse every sixteen clock cycles. If input TESTN is 0, ENA is set to a 1. Variable COUNT is inferred as flip-flops. 

Here the intention appears to be to store the value of PresentState in a flip-flop (rising-edge-triggered). After synthesis, not only is there a flip-flop for PresentState, there are also four flip-flops for Zout. This is because Zout is assigned under the control of a clock. It may or may not be the intention to generate flip-flops for Zout. If not, then a case statement needs to be written in a separate always statement in which Zout is assigned, this... 

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