Gate symbols

The simplest shift-register is the serial I/O type, shown in Figure 23.18 (omitting the dashed-line outputs). The 4-bit register presented is constructed from master-slave clocked flip-flops. (It can also be constructed from JK flip-flops in exactly the same manner but it cannot be constructed from RS flip-flops.) Notice that a shorthand notation, with the AND gate symbols omitted, is used for the clocked flip-flops. 

Fault tree analysis is a very detailed analytical technique for determining the various ways in which a particular type of failure could occur. Fault tree analysis is based on the negative analytical trees discussed in Chapter 10 and uses the same event and gate symbols (Fig. 15-1). 

Logic Cates Elements in a fault tree become related by Boolean algebra. Symbols depict the kinds of relationships among elements. Basic logic relationships are OR and AND, represented by gate symbols. Both AND and OR gate symbols have unique shapes, as shown in Figure 36-4. 

Soft tree analysis is a tool that engineers and software progranuners can both understand. If the engineer is comfortable with fault trees, then it will not take long to feel comfortable with soft tree analysis. The logic gate symbols are the same. It can be used with any software language. NASA uses this method extensively on spacecraft control systans. 

Figure 3.1 Quantum logic gates symbols for one and two-qubit operations. Adapted with permission from [1].

Basic FT gate symbols are shown in Figure 2.27, along with their definition and mathematical formula. 

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