Wafer passivation

Silicon (100) wafers, passivated with silica, were employed as substrates. Prior to immobilization of PLL- -PEG onto the oxide surface, the wafers (0.5 cm 0.5 cm) were prepared by sonication in toluene (2 min) and in 2-propanol (10 min), extensively rinsed with ultrapure water (EM SCIENCE, Gibb-stown, NJ), dried under a gaseous nitrogen flow, and exposed for 2 min to an oxygen plasma (PDC-32G. Harrick Scientific Corp., Ossining, NY). The oxidized substrates were immediately transferred to a 1.0 mg/mL solution of PLL- -PEG in a 10 mM HEPES buffer and incubated there for 40 min. The polymer-coated substrates were then stored in a HEPES solution (in the absence of PLL- -PEG) until use in AFM experiments. Prior to AFM measurements, the polymer-coated substrates were withdrawn from solution, rinsed with a HEPES buffer and ultrapure water to remove free PLL- -PEG, and then dried under a nitrogen flow. 

These processes are considerably more complex in actual CMOS fabrication. First, the lower layers of a CMOS stmcture typically have a twin-tub design which includes both PMOS and NMOS devices adjacent to each other (see Fig. 3b). After step 1, a mask is opened such that a wide area is implanted to form the -weU, followed by a similar procedure to create the -weU. Isolation between active areas is commonly provided by local oxidation of sihcon (LOCOS), which creates a thick field oxide. A narrow strip of lightly doped drain (LDD) is formed under the edges of the gate to prevent hot-carrier induced instabiUties. Passivation sidewalls are used as etch resists. A complete sequence of fabrication from wafer to packaged unit is shown in Figure 10. 

A widely used glass is phosphosilicate (PSG), which is used extensively in semiconductor devices as a passivation and planarization coating for silicon wafers. It is deposited by CVD by the reaction of tetraethyl orthosilicate (TEOS) (C2H50)4Si, and trimethylphosphate PO(OCH3)3, in a molecular ratio corresponding to a concentration of 5 to 7% P. Deposition temperature is usually 700°C and pressure is 1 atm. 

The hrst mechanism specihcally for tungsten CMP was proposed by Kaufman et al. [67]. They thought, first, chemical action dissolves W and forms a very thin passivating him which stops growth as soon as it reaches a thickness of one or a few moleculars later. Second, the him is removed locally by the mechanical action of abrasive particles, which contact with the protrude parts of the wafer surface, and then cause material loss. In recent years, most of the analysis and models for metal CMP are built based on the Kaufman model [68,69]. However, the model is not involved in microscopic structure analysis for the polished surface, but focuses on interpreting macroscopic phenomena happening during CMP [18]. 

Cleaning and the control of surface passivation then became a major issue, because traces of heavy metals in concentrations of less than a thousandth of a monolayer on the surface of a silicon wafer are sufficient to degrade device performance. 

But even in a homogeneously doped material an etch stop layer can be generated by an inhomogeneous charge carrier distribution. If a positive bias is applied to the metal electrode of an MOS structure, an inversion layer is formed in the p-type semiconductor. The inversion layer passivates in alkaline solutions if it is kept at the PP using a second bias [Sm5], as shown in Fig. 4.16b. This method is used to reduce the thickness variations of SOI wafers [Og2]. Illuminated regions... 

Another CMOS-process modification included the deposition of a nitride layer on the wafer backside. The backside nitride is identical with the CMOS passivation. All wafers are already delivered with this backside nitride by the CMOS foundry aus-triamicrosystems. 

Conditions have been defined for applying polyimide coatings onto the silicon wafer as passivation and/or dielectric. Processing variables studied included the critical areas of adhesion, cure cycle and thermostability. Aminosilane was shown to be effective adhesion promoter. The rate of imidization was followed by F.T.I.R. employing time lapse technique. 

It is not too surprising that vapor-phase HMDS also improves adhesion to this substrate. The native oxide has been shown on Y58 wafers to be easily treated and/or passivated. Actual resist image lift testing on vapor promoted polysilicon wafers produced superior results and no image lifting occurred even for first generation resists known to be susceptible to lifting . 

Low-Pressure CVD Processes. Low-pressure CVD (LPCVD) (—101 Pa) is the main tool for the production of polycrystalline Si dielectric and passivation films used in Si IC (integrated-circuit) manufacture (1, 20, 21). The main advantage of LPCVD is the large number of wafers that can be coated simultaneously without detrimental effects to film uniformity. This capability is a result of the large diffusion coefficient at low pressures, which... 

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