Transistor, metallization pattern

One step in a process to manufacture integrated circuits on silicon wafers (computer chips) involves etching the surface with a plasma. The metal layer on the silicon wafer is coated with a polymer template, such that portions of the metal are exposed. A plasma above the silicon wafer selectively etches the exposed metal. When the polymer is dissolved away, a pattern of the protected metal remains. This metal pattern connects electronic devices on the silicon surface, such as transistors and diodes. 

Polymeric materials are used as the basis of photoresists for making metal patterns on printed circuit boards, and also on the individual integrated circuit devices themselves. The circuit boards are made of various glass-fibre filled epoxides and polyesters, and are usually coated with other polymeric materials to prevent tarnishing and to improve solderability. The devices that are mounted on the completed printed circuit boards may have been manufactured using polymeric photoresists or have plastics such as polypropylene and polyester films in capacitors or epoxide resins in integrated circuits and transistors. The completed boards containing various devices are often then coated in another protective polymer. Finally, electrical connections are made... 

The TFTs are made on transparent glass substrates, onto which gate electrodes are patterned. Typically, the gate electrode is made of chromium. This substrate is introduced in a PECVD reactor, in which silane and ammonia are used for plasma deposition of SiN as the gate material. After subsequent deposition of the a-Si H active layer and the heavily doped n-type a-Si H for the contacts, the devices are taken out of the reactor. Cr contacts are evaporated on top of the structure. The transistor channel is then defined by etching away the top metal and n-type a-Si H. Special care must be taken in that the etchant used for the n-type a-Si H also etches the intrinsic a-Si H. Finally the top passivation SiN, is deposited in a separate run. This passivation layer is needed to protect the TFT during additional processing steps. 

Figure 12.5. Photograph of microdispensing system depositing an inorganic dielectric dispersion onto a patterned, metallized polyester film. The pattern is of a transistor gate electrode array. The microdispensing head atomizes the dispersion, generating a liquid spray much like a dual orifice atomizer found on an airbrush.

Figure 15. Simplified process sequence for the fabrication of an NMOS transistor (a) substrate preparation, (b) selective exposure of substrate, (c) mask formation by differential solubility, (d) etching, (e) stripping of resist, (/) doping, (g) reoxidation of silicon surface, (h) formation of gate oxide, and (i) metal deposition and patterning. Abbreviations are defined as follows p-Si, p-type silicon PR, photoresist S, source G, gate and D, drain.

Massive electrochemical attack known as galvanic corrosion [58,59] is the most severe form of copper corrosion. It can completely remove the copper from the structures (Figs. 17.25 and 17.26). It can occur when the wafers are exposed to a corrosive electrolyte for an extended period. It can also occur if the slurry does not contain enough or effective corrosion inhibitor. The source of such a galvanic potential on the patterned copper surface may be due to the fact that some copper structures connected to transistors have a different electrical potential than the rest of the wafer surface. Another possible cause of this type of galvanic potential is related to the barrier material induced metal metal battery effect. Most copper CMP slurries have been developed for Cu structures with Ta or TaN as a barrier material. In some cases, other metals may also be used in addition to the barrier metal. For example, a metal hard mask could contribute to the galvanic corrosion effects. It is also possible that some types of copper are more susceptible to corrosion that others. The grain... 

Computers, microprocessors, and other microelectronic devices could not exist as we know them today without the technology of depositing thin metal or alloy films with fine lithographic patterns. For example, in a computer, the individual transistors that make up an integrated circuit must be electrically interconnected by a complex network of conducting lines and vias that are deposited above the semiconductor layers. Furthermore, the chips are joined to multi-chip packaging modules, a process in which many electrical connections are simultaneously established by solder balls. 

The transition metal complexes shown in Fig. 8-8 thus display a pattern which follows consistently the concepts of two-step electrochemical tunneling and the theoretical formalism above. Mapping and working principles of redox switching and transistor -like behaviour close to the single-molecule level of interfacial electrochemical electron transfer have thus been achieved. This can be compared with biological macromolecules addressed below. 

The purpose of this research was to determine the feasibility of incorporating CPI into field-effect transistors. Due to time limitations and availability of various equipment, source and drains were formed by thermal diffusion rather than by ion implantation as proposed in the preceded discussion. As a result of this slight change in process sequence, metal-gate FETs could be fabricated as a control for the CPI devices. In addition, a non-photosensitive PI was used thus requiring extra photoresist deposition and patterning steps. 

Additional photolithographic steps similar to those discussed earlier are necessary to reopen the silicon dioxide covering source and drain areas above the p-type regions and to create a very thin silicon-dioxide layer below the gate area. The next step involves deposition of a metal such as aluminum to form the contacts for the source, gate and drain. Finally, an interconnection pattern is defined to connect the transistor with other electrical components on the surface. The transistors are now finished and the wafers proceed to other processing operations. 

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