Drain contacts

Figure 14-7. A MISFET in operation, (a) VK>V l/j=0 an n-lypc channel of constant thickness forms at the insulator-semiconductor interlace, (b) V, > V , Vlt - Vy, the channel is pinched ofl at the drain contact. The white area that separates the p-lype substrate from the ii-lypc contacts and channel represents the depletion layer.

Fig. 3 Pentacene grown by supersonic molecular beam deposition to form near monolayer p-type FETs with thiolate monolayer modified Au source and drain contacts (a) visualized by atomic force microscopy and with well-behaved (b) /d-Eds and (c) -Eg characteristics...

Electrostatic bonding of the crystal on top of a previously prepared gate-insulator-source-drain structure [92-94]. Sometimes the source and drain contacts have been deposited afterwards, on top of the crystal [90]. 

In contrast, the channel length of the BCE structure is defined by the source-to-drain contact spacing. While printed features may be large, the spatial control of the droplet placement is very precise, of the order of +5 pm. Combining this control with the BCE TFT structure, a small feature gap can be defined to pattern the source/drain contacts to fabricate a shorter channel device. This structure is more appropriate for fine-feature print-patterned devices. Figure 11.6 shows a schematic comparison of the tri-layer and BCE structure. 

The unwanted Si is etched away and contact holes, "denoted by A in Fig. 3, are etched through the silicon for connecting the drain contact to the ITO pads. The top electrode configuration, S and D, is then formed from the... 

The n+ underlay was used with the source and drain contacts to provide good electron-injecting properties. This caused the reproducibility of the contacts to increase, and the ON current obtained in this way increased significantly. For example, devices with n+ contacts consistently produced source-drain currents a factor of about three higher than the best currents obtained without the n+ layers. 

Values of determined by both the above methods agree to within 10% or better and, at room temperature, were typically 0.2-0.3 cm2 V-1 sec-1 in magnitude. The sample represented in Fig. 12 has a room-temperature mobility of 0.31 cm2 V-1 sec-1 with an activation energy EM of 0.11 eV. Figure 13 shows versus 103/T curves for three devices measured under these conditions, and Fig. 14 summarizes the values of EM as a function of Vc. Curve a in Fig. 14 represents data from earlier samples that did not employ n+ contacts at the source and drain contacts. Curve c represents data from the latest optimized FETs and curve b an intermediate stage in this development. At zero gate voltage, all three curves lead to values of—0.7... 

Figure 16 shows the transfer characteristics of some typical a-Si H FETs used in the experiments, both before and after irradiation. The postirradiation curves have been shifted by the amount of their AVr (stated for each curve) to facilitate the comparison and show clearly the changes produced by the irradiation. It is evident that no major deterioration in performance has occurred in fact, the decrease in transconductance was less than 10% in all cases. When the above-mentioned samples were annealed at 130 °C, with their gate, source, and drain contacts connected together, the FETs returned to their original transfer characteristics and threshold voltages. 

After experimenting with inverted, noninverted, and dual-gate a-Si H TFT prepared with quasi-ohmic Ti-Al source-drain contacts, the author selected inverted TFTs with Ti-Al top contacts (see Fig. 6) for the active matrix. 

Fig. 7. (Top) Schematic layout of the TFT in the addressing matrix. Cross-hatched area is the drain pad and the dotted area is the source contact. The gap between the source and drain contact is bridged by the underlying gate electrode (broken line) and the a-Si H semiconductor (not shown). (Bottom) View of the finished matrix. The small dark strip is a-Si H. The bright central square is the drain pad, doubling as the optical reflector of the guest-host display. Note that the transistor completely surrounds the drain pad.

---