Optimization adders

Fig. 27 (a) Optimized graphene sheet for the realization of a half-adder. Each logical input noted a and [i controls the photoisomerization state of one of the two stilbene groups. Depending on this isomerization state, the overall conductance of the molecule between the three electrodes is modified, (b) Current intensity calculated in the two output electrodes depending on the conformation of the stilbene groups... 

By performing this common factoring, less logic is synthesized (in the above example, only one adder gets synthesized), a logic optimizer can now concentrate on optimizing more critical areas. 

Chan P. K. et al Delay optimization of carry-skip adders and block carry-lookahead adders. In Proc. 10th Computer Arithmetic Symp., Grenoble, S. 154-164, June 1991. 

Hobson, R. F. Optimal skip-block considerations for regenerative carry-skip adders, IEEE Journal of Solid-State Circuits, 30(9) 1020-1024, AdyidlllUdl 1993. 

Allocation assigns each operation, variable, and communication path to a piece of hardware. It naturally falls into three parts functional unit (FU) allocation, register allocation and connection allocation. In high-level synthesis, the main aim in allocation is to share hardware units, i.e., operations can share functional units (ALUs, adders, etc.), variables can be mapped onto common registers, and memories and transfers can share buses and multiplexors. The goal of allocation is to optimize the overall hardware. 

A CATHEDRAL-III-generated data path is built fi-om a set of fast, optimized application-specific units (ASUs). ASUs perform such functions as max, min, sorting, and convolution, and are composed of standard fiuictional units such as adders and shifters. 

Bomble L, Lauvergnat D, Remacle F, Desouter-Lecomte M (2008) Vibrational computing simulation of a fliU adder by optimal control. J Chem Phys 128 064110... 

The removable attribute indicates that Library Compiler knows what function the cell performs, so the cell can be replaced by a combination of other cells during synthesis and optimization. This attribute is usually attached to relatively complex cells, like adder cells, for example. These cells cannot be inferred by DC. 

You have designed a module for a particular block in a design, and wish to re-use this exact same module in another block. However, you require a larger bus width parameter for this module. Further, you wish to use the most optimal implementation based on the bus-width parameter. A typical example, would again be an adder module. For example, in one block you wish the module to be a ripple cany adder of 8 bits, while in another block you wish to use an adder of 16 bits. 

For both constraint generation and data path optimization, it is necessary to estimate sizes and delays. As mentioned previously, it is extremely difficult to estimate sizes and particularly delays accurately at a high level. For example, timing models often assume that chaining operations implies adding the cycle time. However, any carry-type implementation of an adder will allow chaining with very little time penalty (approximately an additional delay of one bit in the... 

The second row was obtained with the FDLS algorithm to obtain the shortest execution time for different allocations. For the 17 and 21 c-step allocations the results were already optimal so the time could not be reduced. However, for the 19 c-step allocation (2 adders and 2 multiplies), the FDLS algorithm produced a schedule requiring one c-step less. This is also an ( timal result with respect to functional unit cost. CPU times were significantly faste than those for the FDS algorithm and varied between one and two minutes. 

The operations have to be mapped onto components in the final circuit. Components are adders or ALUs etc. During the allocation task the number and the types of components are selected which determines the maximum degree of parallelism. Because scheduling optimizes the execution time on the basis of given lesources, the allocation controls the areaAime trade-off between sequential or parallel designs. 

Before exploring the optimization problems with the assumption of omnipotence and omniscience, it is worthwhile to ask whether such a problem is of practical use or is merely an academic exercise. This molecular electronics project is currently in the proof-of-concept phase. Before determining whether it is possible to train a NanoCell with realistic constraints, we are attempting to verify whether it is theoretically possible. If it becomes clear that it is impossible to train a randomly assembled NanoCell as a 2-bit adder, even with the assumptions of omnipotence and omniscience, then there is no point in trying to train one without these simplifying assumptions. Hence, the optimization problem with the supposition of omnipotence is of practical use. 

The simplest version of an adder circuit is shown in Figure 6.1. This description does not introduce any new language elements but it is useful for later comparisons. Note that the input and output signals have predefined signed integer ranges. It is not usually sufficient to define the input ranges and let the outputs determine appropriate upper and lower botmds themselves. If ANSWER was left unconstrained it may use a 32-bit representation. This is synthesizer dependent and redundant outputs will be removed by area optimization. 

A performance (speed) optimization stage in which predefined timing figures had to be achieved. For each adder circuit, the critical path (input to output) had to be less than 5ns. T o compare the structures of circuits with this performance, the area was unconstrained. Alow level of performance optimization effort was always applied first. If the constraint could not be met, medium and then high levels were tried. Only in one case did a circuit fail to meet its target. The level of effort required for each circuit has not been recorded. 

As before, the adder types are separated into three sections - Integer, RC and CLA Within each section both the s3mthesis and optimization results will be discussed together. 

Table 6.1 Logic s)mthesis and optimization statistics for the integer adder and adder/subtractor architectures. Timing constraints were met in each case. No final area constraint was applied...

The S3mthesis of the multiplier will involve the unrolling of the loop. A 2 x2 multiplication means that two identical blocks of hardware will be created to represent the operations in the loop. Just as the synthesizer did not know that it was creating adder circuits with the user-defined ripple-carry adder examples, it does not know that this circuit is a multiplier. Instead, it simply carries out a series of addition and shift operations. Area optimization is Aerefore die only way to spot common elements and combine them. 

Consider for example a call to the Adder procedure implementing the addition of two numbers. Assume the call is used to increment a variable v by one, so that one operand of the addition is v and the other is the constant 1. By expanding the call to Adder, the addition logic can be optimized taking into account that only an increment is needed instead of a full addition. Without in-line expansion such context-based optimization is not possible. 

In-line expand model calls. A model may consist of a hierarchy of calls to other models in the system. For example, an 8-bit adder may call two 4-bit adders cascaded in series. The designer can optionally and selectively replace a model call by its description. By flattening the calling hierarchy, optimization can be performed across the model boundaries. 

---