Adder synthesis / optimization

Allocation assigns each operation, variable, and communication path to a piece of hardware. It naturally falls into three parts functional unit (FU) allocation, register allocation and connection allocation. In high-level synthesis, the main aim in allocation is to share hardware units, i.e., operations can share functional units (ALUs, adders, etc.), variables can be mapped onto common registers, and memories and transfers can share buses and multiplexors. The goal of allocation is to optimize the overall hardware. 

The removable attribute indicates that Library Compiler knows what function the cell performs, so the cell can be replaced by a combination of other cells during synthesis and optimization. This attribute is usually attached to relatively complex cells, like adder cells, for example. These cells cannot be inferred by DC. 

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