Ripple-carry adder

You have several implementations of a certain datapath module (say an adder.) You wish to use a different implementation (the most appropriate with regard to speed and area) in each instance of an adder in the design. For example, you wish to use a cany select adder in one block, but a ripple carry implementation of the same adder in another. 

There are a variety of approaches that could be adopted to implement a user-defined routine such as a ripple-carry adder. 

Uses the ripple carry adder through the operator... 

The carry-lookahead adder is designed to speed up the addition process by overlapping the carry and sum operations. The result is diat tiie 2n logic level ripple-carry arithmetic process is reduced (in practice) to a log n logic level operation. ... 

Table 6.2 Logic s)nithesis and optimization statistics for the ripple carry adder architectures and the signed dataflow structure. Timing constraints were met in each case. No final area constraint was applied...

The best circuit to compare the carry-lookahead adder with is the ripple-carry architecture, RIPPLE I, shown in Table 6.2, as both have 4-bit operation and output an overflow signal. 

The Booth multiplier was selected as it is relatively simple and allows the previously defined ripple-carry adder/subtractor to be used. Also, it is a good method of designing multiplier hardware that must operate on signed numbers. 

The S3mthesis of the multiplier will involve the unrolling of the loop. A 2 x2 multiplication means that two identical blocks of hardware will be created to represent the operations in the loop. Just as the synthesizer did not know that it was creating adder circuits with the user-defined ripple-carry adder examples, it does not know that this circuit is a multiplier. Instead, it simply carries out a series of addition and shift operations. Area optimization is Aerefore die only way to spot common elements and combine them. 

The 16-bit 2 s complement adder design is contained in Figure 8.12. This is an extension of the ripple-carry adders designed in Chapter 6. A ripple-carry adder has been used rather than a cany-lookahead adder and so speed has been traded for area. The adder provides addition, subtraction and comparison operations. 

The adder itself is contained in Figure 8.13. The ARITH UTILS package contains the two procedures RC ADDER and FULL ADDER. The first defines an N-bit ripple-carry adder and the second a single-bit full adder procedure. These procedures are similar to fiiose constructed as functions... 

Map Operators to library models. The description of a model may contain operators such as + and that can be synthesized in a variety of implementation styles. For example, an addition can be implemented using either a ripple-carry adder or a carry-lookahead addo. The designer can selectively replace operators by calls to specific models in a particular library. Any tq)erator that is not mapped to a library model will be implemented by default as combinational logic, with the exception of multiply ( ) and divide C / )> which must always be mapped. 

You have read in your source HDL followed by compile. An add function in the source HDL code mapped to an adder from the Synopsys Design Ware library. The current implementation is a ripple adder (rpl), but you require a carry-lookahead adder (cla) to be inferred. Does one have to start with reading in the source HDL and specifying constraints to chiange the implementation to a cla adder. 

Fig. 4.13 Schematic diagram of the operation of the carry-ripple adder of Stei-glitz, Kamal, and Watson. The particle-bundles (pairs of particles) encode the bits of the two addends, and are labeled A (0,0), B (0,1 or 1,0), and C (1,1). The fast particle, labeled F, effects the addition of each pair of addends. Afer collision with F, the particle bundles encode the result for each added pair, and F propagates the carry bit from each pairwise addition. (Adapted from Steiglitz, Kamal, and Watson, 1988.)...

The trick to implement this carry-ripple adder was to find a set of particles that have the desired behavior. Steiglitz, Kamal, and Watson sketched a graph-search algorithm (not described here) that searches collision tables for particles implementing any desired logical operation via collisions between a fast particle and slow-particle bundles, as in the carry-ripple addition scheme described above. 

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