Adder circuits

Not all the architectural descriptions presented in this section are synthesized and/or optimized. One particular circuit contains no new constructs but is a use l example for demonstrating the process of speed optimization. 

The circuits designed below are primarily adders however, they can be modified to provide a subtraction capability as well. Some examples of these are also demonstrated. 

Three different forms of addition (and subtraction) circuits are demonstrated below. 

In each case, the addition (or subtraction) is of two 4-bit signed numbers giving a signed 4-bit result. In some circuits a carry out or overflow bit is implemented. 

The synthesizer implements the integer arithmetic functions in its predetermined way. As will be seen, this is a sign-magnitude format. The user- 

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Recalling Bennett s and Fredkin s trick to erase the garbage bits, the way in which the reversible logic circuit in figure 6.9 can be made to act as a real reversible serial-adder circuit is to first operate the circuit as shown, store the desired output, and then operate it backwards using the output and all intermediary garbage bits as new input. After all operations are completed in the reverse direction, we will be left with our desired answer stored on the side and with the serial-adder circuit back in its original state ready for another run. 

Fig. 6.9 A conservative-logic realization of a conventional serisJ adder circuit it is built entirely of Fredkin gates. Places along the wires marked with a dot represent unit time delays at those locations. Illustration patterns after [marg88] and [fredkin82]...

One example of such a circuit is the operational amplifier adder circuit, shown in Fig. 6.15. The signal at input A is summed with the signal at input B. This circuit has a variety of uses in communications circuitry. 

Figure 6.16 SPICE equivalent schematic of an op-amp adder circuit.

The outputs shown in Figs. 7.19, 7.20, 7.21, and 7.22 were summed by using the operational amplifier adder circuit shown in Fig. 7.18. The results of the breadboard are shown in Fig. 7.23, with the clock at the top and the staircase waveform at the bottom. The IsSpice, Micro-Cap, and PSpice results are shown in Figs. 7.24, 7.25, and 7.26, respectively. 

A different design, an adder potentiostat, is shown in Fig. (lb). The RE is buffered by a voltage follower (VF) and separate input signals U, U2, such as rectangular pulses, ramps, or sine waves can be mixed. Similarly, 1/d in Fig. (la) can be composed of several signals by an adder circuit (not shown). 

Transmission of 8-bit data in wireless EIT (a) RF Tx/Rx module and (b) schematic of the binary adder circuit. (From Bera T. K. and Nagaraju J., Switching of a sixteen electrode array for wireless EIT system using a RF-based 8-bit digital data transmission technique, ObCom 2011, Part I, CCIS 269, pp. 202-211, 2012. With permission.)... 

By using 16-bit encoder/decoder ICs, the direct transmission of 16-bit data is possible (Figure 30.7) and this eliminates the binary adder circuit required for converting 8-bit data to 16-bit data. A 16-bit data-transmission scheme uses 16-bit encoder/decoder ICs (e.g., GL116 [Glolab Corporation, United States]). The transmitter module transmits the 16-bit serial data for the receiver to be converted to 16-bit parallel data. 

Transmission of 16-bit data in wireless HIT (a) RF Tx/Rx module and (b) schematic of the binary adder circuit. 

The first expression of molecular numeracy was special because people become (and remain) numerate via mysterious, but molecular, processes in their brains. An electronic half-adder circuit has two inputs and two output channels which is the basis of number processing in most electronic computers. Addition needs an AND logic gate for the carry digit and an XOR logic gate for the sum digit (Fig. 2) [ 129,130]. 

An adder circuit is presented in Fig. 3. The output voltage t/add is the sum of all input signals according to... 

Potentiostat, Fig. 3 Adder circuit to compose an input signal from different sources Ui to Un... 

Figure 1.4 Half-adder circuit. A and B are input bits, S the sum and C the carry bit, which is not used in this...

Figure 1.5 The full adder circuit is built from two half adders.

PROBLEMS WITH SOLUTIONS Pl.l - Work out the truth table for the half adder circuit of Figure 1.4. 

P5.3 - A reversible half-adder circuit can be implemented in a three-qubit system, according to the quantum circuit shown in Figure 5.11 [20] That circuit can be implemented by NMR in a quadrupole 7 = 7/2 nucleus system. Let Jti-j represent ideal selective n pulses applied to the transition i — j. Show that the sequence... 

The simplest version of an adder circuit is shown in Figure 6.1. This description does not introduce any new language elements but it is useful for later comparisons. Note that the input and output signals have predefined signed integer ranges. It is not usually sufficient to define the input ranges and let the outputs determine appropriate upper and lower botmds themselves. If ANSWER was left unconstrained it may use a 32-bit representation. This is synthesizer dependent and redundant outputs will be removed by area optimization. 

A performance (speed) optimization stage in which predefined timing figures had to be achieved. For each adder circuit, the critical path (input to output) had to be less than 5ns. T o compare the structures of circuits with this performance, the area was unconstrained. Alow level of performance optimization effort was always applied first. If the constraint could not be met, medium and then high levels were tried. Only in one case did a circuit fail to meet its target. The level of effort required for each circuit has not been recorded. 

The same table shows the data for the INTGR ADDSUB-DATAFLOW model. This is an integer addition or subtraction circuit, the function of which is selected by the MODE input signal. As the statistics indicate, the s)mthesized circuit occupies almost three times the area as tiie single adder circuit. This consists of three elements ... 

RIPPLE3 is a simpler architecture, although the function it calls is more flexible than the function called in RIPPLE I, for example. In this latest architecture, the ripple-cany function can add or subtract the 2 s complemented binary numbers. However, in this case it is called with a constant, (V. This means that the function will only ever be used for addition and so only the required elements of the function need to be s)mthesi2ed. The statistics in Table 6.2 show that the circuit produced is almost as small as the integer adder circuit. 

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