Data path optimizations

For both constraint generation and data path optimization, it is necessary to estimate sizes and delays. As mentioned previously, it is extremely difficult to estimate sizes and particularly delays accurately at a high level. For example, timing models often assume that chaining operations implies adding the cycle time. However, any carry-type implementation of an adder will allow chaining with very little time penalty (approximately an additional delay of one bit in the... 

Figure 12 Final optimized data-path for the answering machine.

Hyunchul Shin and Nam S. Woo, A Cost Function Based Optimization Technique for Scheduling in Data Path Synthesis , Proc. ofICCD 89, pages 424-427, October 1989. 

The initial data path is then optimized, coloring conflict graphs to minimize the number of functional units, registers, and multiplexors. 

IBM s Yorktown Silicon Compiler includes partitioning, scheduling, data path synthesis, design iteration, controller design, logic synthesis, and timing optimization. See also Univ. of Karlsruhe s DSL Synthesis System / CADDY System — Camposano was previously involved with that system, and IBM s HIS System — Camposano is now involved with that system. 

The YIF internal representation, scheduling, data path synthesis, logic synthesis and timing optimization, and a 4-stage IBM 801. 

History, design representation, control step scheduling, data path synthesis, controller generation, logic synthesis, layout design, timing optimization, and the IBM 801. Very detailed. 

A CATHEDRAL-III-generated data path is built fi-om a set of fast, optimized application-specific units (ASUs). ASUs perform such functions as max, min, sorting, and convolution, and are composed of standard fiuictional units such as adders and shifters. 

Zebo Peng, A Horizontal Optimization Algorithm for Data Path / Control Synthesis , Proc. of ISCAS 88, pages 239-242, June 1988. 

Applies transformations to the control step schedule to remove dummy states, and allocates control registers, interface logic, and a finite state machine to build the controller. Optimizations are then applied to reduce the. size of the finite state machine, and to simplify the wiring between the controller and the data path. 

The University of California at Irvine s YHDL Synthesis System (VSS) produces Register Transfer level designs, which can then passed on to the Microarchitecture and Logic Optimizer (MILO) system for optimization and library binding. The VSS includes transformations, scheduling, data path synthesis, and functional synthesis. 

The Univ. of Illinois IBA (Interleaved binder and Allocator) system consists of several parts Illinois Mixed behavior / Structure Language (IMBSL), which performs data path synthesis RLEXT (Register Level Exploration Tool), which allows a user to manually modify a Register-Transfer level design, and then automatically repairs any errors or omissions so that the final result matches the specified behavior, COD, a control unit synthesizer LE (Layout Estimator) and Fasolt, a Register-Transfer level datapath optimizer. See also Univ. of Southern California s ADAM System — Knapp used to be involved with that stem. 

First, an ASAP schedule is constructed, assuming infinite resources, and one cycle per operation. Then optimizations are applied, moving operations to other control steps to reduce the maximum number of operations of each type in any one control step, and grouping operations into functional units so as to have a minimum number of functional units. Uien the scheduler traverses the control step schedule, passing the operations in each control step to the data path allocator. The data path allocator tries to bind those operations using heuristics if it fails, the scheduler tries to delay operations until later control steps, and if that also fails, the user is notified that the resource constraints should be increased. 

Several post-processing optimizations may be run to improve the final data path. Busser is a program used to choose busses and add them to the data path. Other optimizations create special purpose hardware such as increment/decrement registers and constant ROMs. 

Allocation is performed in two separate steps. First, a complete, functional initial data path is generated. The initial data path is then optimized in a second step. Optimizations are based on the well known clique covering [39], and coloring [19] approaches. 

Figure 8 shows the optimized data path for the example. In this case, only two multiplexers could be merged. 

We can state the theorem in other words, omitting the proof. Given a data flow graph and the number of function units available for each type (Mt ), we can realize an optimal pipelined data path with latency / = maxf i... 

Several considerations lead to the definition of the cost functions which we would like to optimize during the course of data path construction. They are categorized according to the associated subtasks. 

The data path binding problem is divided into two phases data path construction and data path refinement. A branch-and-bound search algorithm is used to construct the initial data path based on a set of observations. During the data path refinement phase, we rip up a mixture of variables, data transfers and operations and relocate them. The refinement is augmented with a randomized selection process to prevent itself from being trapped in a local optimal. 

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