Area optimization adders

The simplest version of an adder circuit is shown in Figure 6.1. This description does not introduce any new language elements but it is useful for later comparisons. Note that the input and output signals have predefined signed integer ranges. It is not usually sufficient to define the input ranges and let the outputs determine appropriate upper and lower botmds themselves. If ANSWER was left unconstrained it may use a 32-bit representation. This is synthesizer dependent and redundant outputs will be removed by area optimization. 

The S3mthesis of the multiplier will involve the unrolling of the loop. A 2 x2 multiplication means that two identical blocks of hardware will be created to represent the operations in the loop. Just as the synthesizer did not know that it was creating adder circuits with the user-defined ripple-carry adder examples, it does not know that this circuit is a multiplier. Instead, it simply carries out a series of addition and shift operations. Area optimization is Aerefore die only way to spot common elements and combine them. 

By performing this common factoring, less logic is synthesized (in the above example, only one adder gets synthesized), a logic optimizer can now concentrate on optimizing more critical areas. 

A performance (speed) optimization stage in which predefined timing figures had to be achieved. For each adder circuit, the critical path (input to output) had to be less than 5ns. T o compare the structures of circuits with this performance, the area was unconstrained. Alow level of performance optimization effort was always applied first. If the constraint could not be met, medium and then high levels were tried. Only in one case did a circuit fail to meet its target. The level of effort required for each circuit has not been recorded. 

Table 6.1 Logic s)mthesis and optimization statistics for the integer adder and adder/subtractor architectures. Timing constraints were met in each case. No final area constraint was applied...

---