Logic optimization

Such movement of code should be performed by the designer to produce more efficient code this gives the logic optimizer a better starting point to begin optimizations. 

By performing this common factoring, less logic is synthesized (in the above example, only one adder gets synthesized), a logic optimizer can now concentrate on optimizing more critical areas. 

Constant folding implies the computation of constant expressions during compile time as opposed to implementing logic and then allowing a logic optimizer to eliminate the logic. Here is a simple example. 

Constant folding computes the value of the right-hand-side expression during compile time and assigns the value to Yak. No hardware need be generated. This leads to savings in logic optimization time. 

Experimental studies have shown that logic circuits of size between 2000 to 5000 gates are best handled by a logic optimizer. This implies that in a Verilog HDL model, always statements must not be inordinately long. A design should be structured into multiple always statements or multiple modules. 

Synthesis run-times, mainly logic optimization, are exponential with design size. Thus it is critical to keep the sizes of sub-blocks within a design manageable. 

It is useful to retain the hierarchy of a Verilog HDL model in terms of always statements. This enables a hierarchy of sub-circuits to be produced by the synthesis tool that a logic optimizer can effectively handle. 

Note A logic optimizer has not yet been used it // could potentially remove a redundant gate. 

The synthesized netlists shown in this book are NOT optimized netlists thus the logic shown in some cases may be suboptimal. This is acceptable since the purpose of this book is to show the transformation of Verilog HDL to gates and not that of demonstrating logic optimization... 

Having produced a gate level netlist, a logic optimizer reads in the netlist and optimizes the circuit for the user-specified area and timing constraints. These area and timing constraints may also be used by the module builder for appropriate selection or generation of RTL blocks. 

In this book, we assume that the target netlist is at the gate level. The logic gates used in the synthesized netlists are described in Appendix B. The module building and logic optimization phases are not described in this book. 

Hooker J.N. 2002. Logic, optimization, and constraint programming, INFORMS J. Comput., 4(4), 295-321. 

The examples of table 1 have been synthesized through the two-level logic optimizer Espresso [6], and implemented using a custom PLA generator built in the GDT environment [9]. The results for the three architectures presented in table 2 include the area for state registers, etc. For the stack and register architectures, only the area relative to the original architecture is presented. 

R. K. Brayton et al. Multiple-Level Logic Optimization System. In Proceedings of the IEEE International Conference on Computer-Aided Design, ICCAD-86, Santa Clara, CA, 1986. 

Wang ARR (1989) Algorithms for multilevel logic optimization. PhD thesis. University of Califomia, 1989... 

The University of California at Irvine s YHDL Synthesis System (VSS) produces Register Transfer level designs, which can then passed on to the Microarchitecture and Logic Optimizer (MILO) system for optimization and library binding. The VSS includes transformations, scheduling, data path synthesis, and functional synthesis. 

VaGa88] N. Vander Zanden, D. Gajski, MILO A Microarchitecture and Logic Optimizer, Proc. DAC, 1988. 

The above-mentioned method is generally referred to as Multi-Level Logic Optimization. ... 

In any case, SFLEXP has shown that logic optimization in VLSIs with more than 100,000 gates (that is, VLSIs whose control logic comprise more than 10,000 gate circuits) is possible in practical CPU time. 

With regard to power consumption and occupied area (item a)), SFLEXP has already tried to minimize them in the logical optimization and initial circuit construction phases. Thus, OPTMAP does not make any further attempts to improve them. 

Y. Matsunaga and M. Fujita, Multi-Level Logic Optimization Using Binary Decision Diagrams, ICCAD-89, pp. 556-559, Nov. 1989. 

R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS A multiple-level logic optimization system. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD-6(6) 1062-1081, November 1987. 

The logic optimizer has accomplished several tasks in these examples. It has ... 

Table 5.6 Logic optimization statistics for the process blocks COUNTING and CARRY in the architecture BEHAVIOUR of the up-down counter...

This is where the optimizer is very useful. If Figure 6.29 is examined, it can be seen that the logic that now remains implements die simple Boolean equations of a 2 x2 multiplier. For example, RESULTO is just (AO and BO), although it is implemented with the faster but equivalent Nand logic. This example has really illustrated the power of the logic optimizer. 

Table 7JZ Logic optimization statistics for the processes in the Decoder component (DECODER BEHAVIOUR) and Enabler block (SEQUBMCE-BEHAVIOUR)...

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