Modeling Hardware Behavior

HardwareC assumes that the design is non-pipelined. In executing a process the control flow propagates from the first statement in the process to the last statement. Non-pipelined implementation means that the first operation in the process can be re-executed only once the last operation in the process has completed in the previous execution. Each time process is restarted, a statement in the process is executed at most once. Although the language does not directly support pipelined descriptions, each pipe-stage can be described as a separate process, where the interconnection of these pipe-stage processes forms the pipeline. 

In HardwareC, hardware is modeled as a collection of concurrent modules. Each module represents functionality that can be described either as a structural interconnection of components (i.e. declarative semantics) or as a set of operations sequenced in time that performs a particular algorithm (i.e. imperative or procedural semantics). 

Modeling hardware behavior as a collection of concurrent and intoacting processes is natural for hardware description since hardware modules continuously operate on a time varying set of inputs. Therefore, blocks describe the structural relationships among the processes, which in turn describe algorithms containing a hierarchy of procedures and functions. Processes allow coarse-grain parallelism to be specified at the functional level. 

Message passing via explicit blocking send and receive operations can be used for both synchronization and data-transfer. Information transfer takes place 

Block and process models can only have global ports and channels. For procedure and function models, both local and global ports are allowed in addition to channels. 

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Model the behavior of hardware and software components that make up the system... 

Static and dynamic approaches have different trade-offs. Static approaches have, in principle, the benefit that results can be obtained without test harnesses and environment simulations. On the other hand, the dependence on a hardware timing model is a major criticism against the static approach, as it is an abstraction of the real hardware behavior and might not describe all effects of the real hardware. In practice, tools suppwrt a limited number of processors (and may have further restrictions on the compiler that is used to produce the binary to be analyzed). Bemat et al. (2003) aigyies that static WCET analysis for real complex software, executing on complex hardware, is "extremely difficult to pierform and results in rmacceptable levels of pessimism." Hybrid approaches are not restricted by the hardware s complexity, but nm-time measurements may be also difficult and costly to obtain. 

The input to the structural synthesis phase consists of a sequencing graph model of the hardware behavior to synthesize, along with the following constraints, which can either be specified in the input hardware description, or entered in-tCTactively by the designs. 

We overview in this chapter the hardware modeling language and synthesis flow in Hercules and Hebe. Section 2.1 describes the modeling of hardware behavior using HardwareC [KM90a]. HaidwaieC supports constraint specification and ext ual synchronizations. Section 2.2 presents a brief overview of the ovoall synthesis flow in Hercules and Hebe. 

To define the cost function that will drive the control optimization, we briefly outine the mapping from a constraint graph model of hardware behavior to a control implementation. The details are presented in Chapters 6 and 8 we summarize in this section the major results as background for defining the control optimization criterion. 

We can arrive at our theories in two main ways. In the first, as illustrated earlier, we subject a system to experimental perturbations, tests, and intrusions, thereby leading to patterns of observables from which we may concoct a theory of the system s structure and function. An alternative approach, made possible by the dramatic advances that have occurred in the area of computer hardware in recent times, is to construct a computer model of the system and then to carry out simulations of its behavior under different conditions. The computer experiments can lead to observables that may be interpreted as though they were derived from interactions. 

If there are external components—software or hardware—that define objects you need to use, spin off a task to evaluate whether to use these objects exactly as defined or whether to build a layer that offers a model closer and more natural to the one you would like to use internally in your development. If a core component defines widely shared and widely used objects, you may need to design a generic architectural scheme for extensible object data and behaviors. 

This book is a compilation of all various types of electronic circuits. Such compilations are not unusual in fact, there are several excellent circuit encyclopedias on bookshelves. However, this book goes several steps further. Instead of simply presenting the circuit to the reader, it also provides a SPICE schematic and details about the equivalent hardware performance. The intricacies involved in developing an accurate SPICE model of the circuit are also included. This format benefits readers in numerous ways. First, it allows them to emulate the correlation techniques introduced in this book in order to make their own SPICE models accurately mimic the behavior of the hardware. Secondly, it allows them to clearly see where SPICE excels in its ability to represent real hardware performance. 

The Verilog Hardware Description Language, often referred to as Verilog HDL, is an IEEE standard (IEEE Std 1364). The language can be used to describe the behavior, sequential and concurrent, or structure of a model. It can support the description of a design at multiple levels of ab-... 

Computational quantum mechanics continues to be a rapidly developing field, and its range of application, and especially the size of the molecules that can be studied, progresses with improvements in computer hardware. At present, ideal gas properties can be computed quite well, even for moderately sized molecules. Complete two-body force fields can also be developed from quantum mechanics, although generally only for small molecules, and this requires the study of pairs of molecules in a large number of separations and orientations. Once developed, such a force field can be used to compute the second virial coefficient, which can be used as a test of its accuracy, and in simulation to compute phase behavior, perhaps with corrections for multibody effects. However, this requires major computational effort and expert advice. At present, a much easier, more approximate method of obtaining condensed phase thermodynamic properties from quantum mechanics is by the use of polarizable continuum models based on COSMO calculations. 

Several sophisticated techniques and data analysis methodologies have been developed to measure the RTD of industrial reactors (see, for example, Shinnar, 1987). Various different types of models have been developed to interpret RTD data and to use it further to predict the influence of non-ideal behavior on reactor performance (Wen and Fan, 1975). Most of these models use ideal reactors as the building blocks (except the axial dispersion model). Combinations of these ideal reactors with or without by-pass and recycle are used to simulate observed RTD data. To select an appropriate model for a reactor, the actual flow pattern and its dependence on reactor hardware and operating protocol must be known. In the absence of detailed quantitative models to predict the flow patterns, selection of a model is often carried out based on a qualitative understanding of flow patterns and an analysis of observed RTD data. It must be remembered that more than one model may fit the observed RTD data. A general philosophy is to select the simplest model which adequately represents the physical phenomena occurring in the actual reactor. 

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