Instantiation Statement

A module instantiation statement can be written within a module declaration. A synthesis system treats such a module instance as a black box and does not take further action, that is, the module instance appears in the synthesized netlist as if it were a primitive component. Here is an example of a full-adder module that contains one module instantiation statement. Notice that in the synthesized netlist, shown in Figure 2-67, the module MyXor appears just as it is described in the top level module FullAdderMix. 

The above module instantiation statement replaces the // following always statement ... 

Here is another example. This is a 3-bit up-down counter that shows how a pre-built D-type flip-flop is used along with its remaining behavior. The key statements that are necessary to be added are the module instantiation statements. With such a model, a synthesis system retains the prebuilt component in the synthesized design to achieve the desired result this is shown in the synthesized netlist. 

Sequential logic elements, that is, flip-flops and latches, can be inferred by writing statements within an always statement using styles described in Chapter 2. It is best not to synthesize a memory as a two-dimensional array of flip-flops because this is an inefficient way to implement a memory. The best way to create a memory is to instantiate a predefined memory block using a module instantiation statement. 

A memory is best modeled as a component. Typically, synthesis tools are not efficient at designing a memory. More traditional techniques are generally used to build a memory. Once having built this module, it can then be instantiated in a synthesis model as a component using the module instantiation statement. 

A component instantiation statement creates a unique occurrence or instance of a particular component within an architecture. The statement... 

The architecture identifier is optional when directly instantiating a component. If it is provided, the name must match that of the secondary unit (the architecture) associated with the specified primary unit (the entity) in the instantiation statement. If it is not provided, the synthesizer will look in the WORK and any other visible libraries in sequence for the specified entity. The architecture associated with that entity will be automatically selected. This may lead to the incorrect component behaviour if the same entity identifier occurs in several different libraries. 

The architecture body illustrates another way to instantiate components in a design. Again, there are no component declaration statements in the architecture s declarative part. However, this time these declarations do not even exist in a package. Instead, the components are directly instantiated by specifying the name of the entity and architecture (in parentheses) in the component instantiation statement. The port list follows in the normal way. 

Although it is feasible to create a small circuit with individual component instantiation statements, constructing port maps for large numbers of components is a tedious and error-prone exercise. If, as in this example,... 

Fortunately, to enable some flexibility, a range of type conversion functions are available within standard IEEE and vendor tibraries diat will allow conversion between types. These can be of particular benefit when using old components or modules in a design that was created using different types. The only restriction set by many synthesizers is that type conversion cannot be done in the component instantiation statement. 

Bodi conversion functions and strengdi strippers can be used like normal functions. The only exception to this is that some synthesizers may not allow them to be used in parameter lists when calling other fimctions or procedures. Additionally, neither function can be called in the port map of a component instantiation statement. 

A type conversion or any other function is not supported in a component instantiation statement. Fimction calls are supported when nested in other functions or procedures. 

The Kaplan-Meier survival estimates plots are instantiated by specifying PLOTS = (S) in the PROC LIFETEST statement. To show just the line itself, CENSOREDSYMBOL = NONE is specified to hide the censored observations in the plot. EVENTSYMBOL = NONE is specified here to hide the event points, although this is the default setting for... 

PROLOG tries again to match the input statement with the entries in the data base. The variable Compound is instantiated to whatever object happens to occupy the respective position in the data base entry. If a match is found, the value assigned to the variable is put out. In our example the result (its presentation may again vary slightly with different implementations) will be... 

A list can be assigned to a variable, i.e. a variable can be instantiated to a list. Furthermore, the operator serves to separate the head of a list from its tail. Thus, the PROLOG statement... 

CP-nets are similar to Bayesian networks [17]. Both utilize directed graphs however, the aim of CP-nets in using the graph is to capture statements of qualitative conditional preferential independence. A CP-net over variables V = Xi,..., Xm is a directed graph G over Xi,..., Xm whose nodes are annotated with conditional preference tables CPT Xi) for each X G V. Each conditional preference table CPT Xi) associates a total order with each instantiation u of Xj s parents Pa Xi) = U [5]. 

Because the potential instantiations of a strictly universal statement are infinite, the statement is never verifiable. (Some will restrict that conclusion to intensionally defined universal [e.g., defined on the basis of some descriptive criteria], but Popper showed [1976 14] that universals can also be pointed at [i.e., ostensively defined] if a particular [individual] is pointed at in a statement that adds and other similar things or and so However, if a singnlar statement reporting on an observable state of affairs that... 

---