Module instantiation statement

A module instantiation statement can be written within a module declaration. A synthesis system treats such a module instance as a black box and does not take further action, that is, the module instance appears in the synthesized netlist as if it were a primitive component. Here is an example of a full-adder module that contains one module instantiation statement. Notice that in the synthesized netlist, shown in Figure 2-67, the module MyXor appears just as it is described in the top level module FullAdderMix. 

The above module instantiation statement replaces the // following always statement ... 

Here is another example. This is a 3-bit up-down counter that shows how a pre-built D-type flip-flop is used along with its remaining behavior. The key statements that are necessary to be added are the module instantiation statements. With such a model, a synthesis system retains the prebuilt component in the synthesized design to achieve the desired result this is shown in the synthesized netlist. 

Sequential logic elements, that is, flip-flops and latches, can be inferred by writing statements within an always statement using styles described in Chapter 2. It is best not to synthesize a memory as a two-dimensional array of flip-flops because this is an inefficient way to implement a memory. The best way to create a memory is to instantiate a predefined memory block using a module instantiation statement. 

A memory is best modeled as a component. Typically, synthesis tools are not efficient at designing a memory. More traditional techniques are generally used to build a memory. Once having built this module, it can then be instantiated in a synthesis model as a component using the module instantiation statement. 

Fortunately, to enable some flexibility, a range of type conversion functions are available within standard IEEE and vendor tibraries diat will allow conversion between types. These can be of particular benefit when using old components or modules in a design that was created using different types. The only restriction set by many synthesizers is that type conversion cannot be done in the component instantiation statement. 

The input to the Workbench is a mixed behavioral and structural description. In Verilog, sequential behavior is described with the always statement, combinational behavior is described with the continuous assignment statement assign), and hierarchical structural is described with module definitions, and module and gate instantiations. For the purposes of the Workbench, the synthesis tools treat the always statement as a single process description of the behavior to be synthesized into a structural data path and controller. For each always statement, a separate controller and data path is generated. 

Workbench. That is, these structural components are not synthesized by the Workbench. However, they define the implicit ports (connections to a continuous assignment and instantiated submodules), and explicit ports (declared ports of the current module) between the behavior described in the always statement and these structural entities. 

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