Architecture body

A design entity contains an entity declaration and an architecture body. These are described in detail below. Figure 3.1 shows the organization of the VHDL design hierarchy and illustrates the main elements of an architecture body. The port connections, indicated by arrowheads, enable information to be passed between blocks and, at the top level, allow the design entity to communicate with the external environment. A design entity may contain any or all of the elements shown in the diagram. It will always have an entity declaration and architecture body at the top level. 

The entity header can contain a generic statement. For synthesis, this defines constants that can be accessed by the port statement or the architecture body. A generic list (Chapter 5) is contained inside the generic statement, which has the syntax ... 

The architecture body is used to specify the relationship between the inputs and outputs declared in the entity. It iherefore describes the actual function of the hardware. Although each entity must be unique, several architectures can be associated wiA one entity. This allows the function of a block to be changed without changing its external structure. The syntax of the architecture body is detailed in Box 3.2. 

The architecture body contains any number of concurrent statements -components and internal blocks are also of this type. These statements can be considered to be executing asynchronously and completely independently of each other. It is therefore crucial to understand how the relationships between different concurrent statements are going to affect not only the behaviour but also the logical structure of the hardware that synthesis will produce. 

The architecture body contains the description of the function of a circuit block. It has the following syntax ... 

The architecture body specifies which components are contained in a design and how they are interconnected. The main VHDL topics associated with structural style architectures include the following ... 

The entity declaration and architecture body are a pair of design units that enable the function and structure of a circuit to be described. 

The Port statement spedfies the names, mode and types of the interface signals in the multiplexer. A name given to any item, from a port signal to an architecture body, must follow a certain convention if the design is to synthesize correctly. These limitations are discussed in Box 4.1. 

The architecture body describes the function of the multiplexer circuit using a dataflow, behavioural or structural design style. An architecture must... 

Four architecture bodies have been constructed using concurrent signal assignments in the dataflow style. These are shown in Figure 4.3. 

Three different architecture bodies have been designed in the structural style for the multiplexer example. The components in each one are as follows ... 

The entity declaration and architecture body of each component is shown in Figure 4.9. Again these descriptions are compiled and stored in the working library where the multiplexer architecture, STRUCTURAL2, can access them. Unlike STRUCTURAL , however, this architecture does not declare the components in its declarative part. Instead it uses a package declaration to store the component declarations. A Use clause is then required to... 

The architecture body illustrates another way to instantiate components in a design. Again, there are no component declaration statements in the architecture s declarative part. However, this time these declarations do not even exist in a package. Instead, the components are directly instantiated by specifying the name of the entity and architecture (in parentheses) in the component instantiation statement. The port list follows in the normal way. 

A function is flexible. As the package body of ARITH TYPES shows, the parameters passed and returned from a function do not have to be constrained. If die function is designed without constraints it can be used in many different designs or several times in the same one, performing operations on n-bit objects. To achieve this flexibility, attributes are used to provide information about each object passed to the function. The RIPPLE functions use the Left and Reverse.ramge attributes discussed further in Box 6.3. A component, on the other hand, is constructed from an entity declaration and an architectural body. This means that the size of each I/O path must be determined at tfie component s compile time, reducing its flexibility. 

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