Damascene copper process

From an historical perspective, it is interesting to note that there are subsequent references to bump formation or superleveling in the former-Soviet literature, although no mechanistic explanation of the phenomena was offered [317-319]. The observation of bumps above filled features was also the first indication that leveling models could not explain superfilling of sub-micrometer features in the Damascene copper process [333-335], Driven by this observation the area change mechanism [66-68] was rediscovered in 2000-2001 by researchers as the CEAC mecha-... 

The 64k, 80 pm x 80pm sized tilting mirrors are built on the top of a CMOS-based control ASIC. In order to reduce the topography of the underlying metallization/passivation structures, a 2.5pm-thick PECVD oxide film is first deposited on the ASIC. An ILD oxide CMP step based on Klebosol 30N50 colloidal silica slurry is used for planarization. In order to connect the ASIC with the deflection electrodes above (see Fig. 14.10), vias have to be etched into the planarized dielectric film. Then, a copper metal stack including a TaN barrier has to be deposited and a two-step Cu damascene CMP process has to be performed. As this process is equivalent to Cu damascene in microelectronics fabrication, standard Cu CMP slurries can be used. 

The damascene copper interconnects are produced by electrodeposition of copper onto PVD Cu seed layer. The electrodeposition of copper layer is carried out to fill in vias and trenches and consequently to form the metal interconnects. The bottom-up fill of copper in fine via holes as schematically presented in Fig. 4 has successfully been demonstrated by Wang et al.37 using the electroless deposition process. 

Figure 16.19 Process steps for dual damascene copper interconnect formation (a) ILD oxide (Si02) deposition by means of PECVD (b) silicon nitride (SiN) deposition...

A production process has recently been implemented by IBM. The aim was to reduce the electrical resistance of the interconnects in their chip to about one-third of the values attainable using aluminum and at the same time increasing the resistance against electromigration. This was made possible by employing electrodeposition of copper in a Damascene method. The manufacturing sequence is presented in Figure 17.11. 

The acceptance of chemical mechanical planarization (CMP) as a manufacturable process for state-of-the-art interconnect technology has made it possible to rely on CMP technology for numerous semiconductor manufacturing process applications. These applications include shallow trench isolation (STI), deep trench capacitors, local tungsten interconnects, inter-level-dielectric (ILD) planarization, and copper damascene. In this chapter. 

The first generation of the interconnect material is aluminum with a resistivity of p = 2.66 pQ cm. One approach to reduce RC delay is to switch to an interconnect material with lower resistivity as indicated by Eq. (1.1). A wide range of metals was considered as a potential candidate in the early 1990s. Gold has excellent resistance to corrosion and electromigration but its conductivity is similar to that of aluminum. Silver has the lowest resistivity (p = 1.59 pQ cm) but poor resistance to corrosion and electromigration. Hence, copper that has a resistivity of 1.67 pO cm and excellent resistance to electromigration was selected. Compared to aluminum, copper has one drawback. It cannot be deposited by RIE. Therefore, a copper interconnect is typically formed via a damascene process in which a pattern is first etched into the dielectric and overfilled with copper. The excess copper above the... 

Other than the damascene process, is there any other way to form microstructures such as copper lines, tungsten vias, and STI ... 

Aruanchalam V, Smith G, Kailasam S, Knorr A, Hettiaratchi K, Rozbicki R, Pfeifer K, Ho P, Pyun J. Comparison of barrier-first and argon pre-clean first processes for copper metallization in ultra low-k (ULK) dual damascene integration. Proceedings of the Advanced Metallization Conference 2005 p 413-419. 

To this point we have discussed recent model extensions in the context of oxide CMP. As illustrated schematically in Fig. 1, dishing and erosion concerns in copper damascene processing also... 

Copper has emerged as the leading contender for back-end-of-line metallization for advanced integrated circuits. Lack of a viable copper etch process and depth-of-focus limitations of advanced lithography leads to the chemical-mechanical polishing (CMP) of Damascene structures as the preferred method by which copper-based metallization is formed. CMP is the only known feasible method by which copper metallization can be patterned to the requisite, feature size and global planarity. 

The top and the bottom coils were fabricated using a damascene process. Coil trenches were formed in a SiO insulating layer using reactive ion etching. A seed layer for electrodeposition such as a Cu/Ti stacked layer was sputter-deposited onto the etched surface. Then, the Cu electrically conductive material was electrodeposited on the seed layer using generic copper sulfate solution. Finally, lapping was performed... 

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