Clock Skew

In the new design, we use two H-trees to deliver clock signals for the top level chip and bottom level chip, respectively. The two H-trees are interconnected through 128 inter-chip contacts to reduce clock skew. 

R eport Paths U sing Advanced D esign Analysis ( Repgrt Paths in Timing Constraints C Report Paths Failing Timing Constraints Analyze Clock Skew for All Clocks... 

Prior work in retiming also includes the ASTRA [6] algorithm, which is a faster approach. It relates the problem of clock skew optimization at each flip-flop to a retiming solution for min-period retiming, and uses the Bellman Ford algorithm to derive the longest path. Recently, the authors of [7] used program derivation to... 

An algorithm to reduce the maximum latch displacement due to clock skew constraints by strategically inserting additional LCBs. 

Use a robust clock scheme to ensure that the entire system is free of race conditions and has minimal tolerable clock skew. 

FIGURE 8.3 An example of race condition caused by a severe clock skew in the system. 

Clock skew A phase difference between two clock signals at different part of a chip/system due to imbalance of the distribution media and the distribution network. 

H-tree A popular clock distribution tree topologically that resembles the H shape. It introduces the least amount of clock skew compared to other distribution topologies. 

Electrical parameters of interconnects (controlled-impedance design, cross talk, clock skew, signal propagation delay, electromagnetic interference for RE circuits, etc.)... 

For the interconnection of digital semiconductor devices, a major issue that must be considered is clock skew, which results from varying the length of clock lines and is a major design consideration for high-speed products. 

Hold time problems will generally occur in shift register structures or scan chains. Since by default DC treats the clock as ideal with no path delays, one must account for the network delay by using the set clock skew -propagated command. 

To specify clock delay or skew on the clock line, use the command set clock skew. The options available with this command are -delay which specifies an absolute delay, -propagated which causes DC to dynamically calculate the delay on the clock line, and the -uncertainty option which specifies the plus or minus skew possible on the clock line. By default, DC will always perform the most restrictive setup check which, in this case, is from 0 to 3. The clock waveforms must be aligned for correct setup check from 10 to 20 as shown in Figure 5.10. Another alternative, if you wish to maintain the clock waveforms is to use the following command ... 

There is no command to specify infinite drive on an internal pin. Infinite drive can only be specified on primary inputs. Use the set clock skew -delay command to specify the actual delay on the clock network. This is usually provided by the ASIC vendor. This will prevent DC from calculating the delay on the clock line, due to transition delays and loading. 

Clock skew in the scan path could result in a scan pull-through or a diverging scan chain. In other words, during the scan shift phase, due to clock skew the same scan bit can be loaded into two successive scan cells. 

The set scan path command can be used to specify which scan chain the flops in a sub-design must be assigned to, depending on the clock skew on that branch. Further, this command can also be used to explicitly order scan cells within a scan chain. This command provides a means to arrange the scan-cells in the scan-chain in the order of reversed skew. 

Retiming latches can be used in the scan chain where there are hold problems identified on the scan path (Q -> Si), due to mixing of clocks or clock skew. One configuration of retiming latches is supported by TC. TC by default, automatically adds retiming latches when mixing clock domains on a scan chain or when manually specified by the user. 

In designs where there are multiple clock domains and datapaths between the clock domains, TC will place clocks in separate capture clock groups, provided they are independent clocks sources in the testmode and not multiplexed to one test clock. Further, the clock skew must be accounted for in the clock waveforms. 

During functional mode timing analysis, there might be multi-cycle paths between the flip-flops. In the test-mode, all the flip-flops are clocked in the same cycle. Hence, perform timing analysis on the complete design after scan-insertion, without any path exceptions. Also, use the set clock skew command to account for all the delays on the different clock branches. If the clock tree is in place, use the set clock skew -propagated command. 

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