Scan Chains

We believe that 2.5-D DFT techniques should be developed to resolve the above problems. The test data compression technique would be essential to test a partial netlist with a large number of inter-chip contacts based I/O. Extra testing circuitry should be inserted so that compressed test results can be accessed through conventional testing pads (e.g., on the boundary) of a chip. Meanwhile, scan chains... 

Epoxy resin (a) Indentation for hardness (b) Spectroscopy (ATR-FTIR) (c) Differential scanning Chain scission Presence of nanofiller -noa in the [163]... 

Figure 1.8 Scan Chain Connected to Form a Shift Register...

Hold time problems will generally occur in shift register structures or scan chains. Since by default DC treats the clock as ideal with no path delays, one must account for the network delay by using the set clock skew -propagated command. 

Figure 8.2 Scan Cells Linked to form a Scan Chain...

When scan cells are linked to form a scan chain as shown in Figure 8.1, all the scan cells are controllable and observable. Since shifting of data into the scan chain is performed serially, it takes N clock cycles to shift an entire pattern into the scan chain, where N is the maximum length of the scan chain. Configurations with multiple scan chains are supported by most synthesis tools. 

Is there a limit on the number of scan chains allowed ... 

The total number of scan bits is simply the number of scan vectors multiplied by the number of flip-flops in the scan chain. 

The insert scan command replaces the non-scan sequential cells with scan equivalent cells and connects the scan cells to form a scan chain. 

Specify the test methodology, scan style, number of scan chains, mixing of clock domains in the scan chain etc. using the set scan configuration command. 

The default test protocol inferred by TC has four phases Scan Shift, Parallel Measure, Parallel Capture, and Scan-Out Strobe. Each test pattern has all these phases. The length of the scan shift phase is equal to the length of the longest scan chain in the design. The remaining three phases are of one cycle with the test clock being pulsed in only during scan shift and the parallel capture cycle. Shown below are the values of the bi-directionals in the different phases ... 

Clock skew in the scan path could result in a scan pull-through or a diverging scan chain. In other words, during the scan shift phase, due to clock skew the same scan bit can be loaded into two successive scan cells. 

The set scan path command can be used to specify which scan chain the flops in a sub-design must be assigned to, depending on the clock skew on that branch. Further, this command can also be used to explicitly order scan cells within a scan chain. This command provides a means to arrange the scan-cells in the scan-chain in the order of reversed skew. 

Retiming latches can be used in the scan chain where there are hold problems identified on the scan path (Q -> Si), due to mixing of clocks or clock skew. One configuration of retiming latches is supported by TC. TC by default, automatically adds retiming latches when mixing clock domains on a scan chain or when manually specified by the user. 

Consider a design with a scan chain and two clock trees as shown in Figure 8.6. Notice that the upstream flip-flops are driven by clock branch C1, and the downstream flip-flops by clock branch C2. When going from clock domain C1 to clock domain C2, a retiming latch is inserted between the scan-out pin of the last flop in the scan chain clocked by C1, and the scan-in pin of the first flop in the scan-chain clocked by C2. The enable of the latch is connected to C1 such that it is transparent when C1 is low. The latch holds the previous scanned value for the duration when the clock pulse is high. This approach works, provided the skew is not greater than the high pulse width of the clock. Alternatively, one must use DC to insert delays to frx the hold time violations. 

By default, TC allocates all scan cells clocked by the same clock, to the same scan chain. Also, scan cells clocked by different edges of the clock are placed in different scan chains. Hence, if one has only one test clock in the testmode, because of multiplexing the functional clocks, TC will place all the scan cells in the same scan chain, by default. 

You are attempting to insert an approximately 70 cell scan chain deep within the hierarchy of the chip. The hierarchy is shown in Figure 8.10. 

Design D contains the 70 cells you wish to scan. When you set the current design to D and generate vectors, it appears that TC naturally has control over all the primary inputs to D and observability of Ds outputs. This, however, is not the case. The only access TC has to inputs and outputs of D, is through a scan chain that was inserted into D. This scan chain has it s serial input through a port in design A, as well as a serial-out, also in design A. 

You read in an ASCII VHDL netlist for your ASIC with the JTAG logic included into TC. The scan chain specific infonnation such as scan-in, scan-out, scan-enable are specified along with other test mode assertion conditions. How to go about handling the included JTAG logic in the design ... 

You have generated test patterns for a design and formatted the vectors in the WGL format. The expected response for the first scan cell in the scan chain is always X (not strobed). Why Shown below is the relevant section from the patterns. 

In the default test protocol inferred by TC, the last scan cell in the scan chain is strobed in the scan-out strobe cycle after the parallel capture cycle. If this is not the case, the next scan-shift cycle will overwrite the captured response in the last scan cell before it is strobed. Hence in the last cycle of the scan shift there is no expected response, that is an X. 

In designs where a functional port is shared with a scan-out port, TC synthesizes a mux to select between the last scan cell in the scan chain and the functional logic. The scan-enable signal is connected to the select line of the mux such that when the scan-enable is active, the last scan cell is selected. Since the scan-enable is generally inactive in most patterns to capture faults on the data path, a separate scan-out strobe cycle is required. 

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