Race condition

Arithmetic operations as conditional expressions, as in the previous example, should be avoided when inferring latches since there is a very high probability of race condition between the conditionals in the synthesized netlist this might cause the latched value in the synthesized netlist to differ from that in the Verilog HDL model. 

Information exchange processes in a communication infrastructure can be modeled as transactions that have to fulfill the ACID properties. If a transaction does not properly proceed and finish, the ACID properties provide a direct categorization of the related anomaly. Based on this categorization, appropriate and effective countermeasures can be applied. A direct violation of the atomicity property, for example, corresponds to a denial-of-service attack, as the transaction is not completed and therefore the requested service is not provided. A buffer overflow represents a violation of consistency, and a race condition a violation of isolation. Other attacks can be classified accordingly. The corresponding anomalies can be detected by comparing protocol and process runs with the given specifications, which are represented by extended finite state machines. 

Fig. D.6. (a) A simple T-flip flop implemented using NAND gates (b) the symbol for a T flip-flop. Q is the output, Q is the inverse of the output. When a rising clock edge is applied to T, the state switches from on to off or vice versa. More sophisticated latches may be necessary to prevent race conditions depending on the transistors used.

Pseudocode iUustrating a race condition in a multi-threaded program. Two threads are created, each reading and modifying a datum at the same memory location, datu m. 

Outcomes for three of the possible code paths that may arise due to the race condition in Figure 4.2... 

Carefully check to avoid deadlock and race conditions... 

If a small number of restrictions are put on the implementation, it is also possible to identify storage elements using the extracted logic equations. The restrictions are basically that the transistor network should be synchronously clocked and free from race conditions, restrictions that are met in most designs. 

Safe tasking is promoted by the Ravenscar profile, which defines a deterministic and certifiable tasking subset, providing the high-level abstraction and expressive power needed for making software easy to design and test. Major hazards related to tasks terminating silently and potential race conditions at elaboration time have been addressed by new mechanisms added to Ada 2005. 

The initial choice of Spin is motivated by its suitability to model threads, their interaction and verify properties related to race conditions and deadlocks (which is the common sources of OS-related bugs). Other modeling formalisms might be more suitable for different goals. 

Given that there are no critical race conditions, that only one input at a time is changed, and that no changes are initiated unless the system is in equilibrium, the state table or state diagram allows the prediction of the behavior of the system for the specihcation of the input sequence and the initial state. An example is given in Fig. 1.78. 

Use a robust clock scheme to ensure that the entire system is free of race conditions and has minimal tolerable clock skew. 

FIGURE 8.3 An example of race condition caused by a severe clock skew in the system. 

SUTURE does not attempt to generate a correct circuit directly, but rather builds it up incrementally by beginning with a skeletal design that will have timing violations and race conditions. The circuit is modifled in a series of local transformations to correct these problems. Only small primitive elements (i.e., logic gates, flip-flops, and latches) are used to assemble the circuit initially so that sequential transformations can later be more easily applied to reduce the overall size of the logic. The four principal steps of the synthesis method are outlined below. 

Race elimination. Race conditions can exist in the circuit because there was no accounting for the period of time for which a signal stays at a particular logic level between events. Three types of race conditions are possible not enough time to synchronize an event before another on the same wire cancels it out a set or reset AND condition that may never be true because one of the input events is followed too closely by another on the same wire and a set or reset condition that is true at other times during the sequence of events and will cause an unwanted setting or resetting to occur. 

The requirement that a control element can initiate execution only in the ready state ensures that no race condition arises as we execute a sequence of... 

Computers are now increasingly being introduced into safety-critical systems like nuclear power plants and aircraft and, as a consequence, have been involved in a number of deadly mishaps. A particularly noteworthy medical example concerns a computerized radiation therapy machine called the Therac-25 used to treat cancer patients. In 1986, two cancer patients died when they received lethal doses of radiation from the Therac-25 system utilizing a computer-based controller. An investigation revealed that one contributor to this catastrophe was failure of the design team to recognize a race condition, a miscoordination between concurrent tasks. 

---