Retiming latches

Retiming latches can be used in the scan chain where there are hold problems identified on the scan path (Q - Si), due to mixing of clocks or clock skew. One configuration of retiming latches is supported by TC. TC by default, automatically adds retiming latches when mixing clock domains on a scan chain or when manually specified by the user. 

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Consider a design with a scan chain and two clock trees as shown in Figure 8.6. Notice that the upstream flip-flops are driven by clock branch C1, and the downstream flip-flops by clock branch C2. When going from clock domain C1 to clock domain C2, a retiming latch is inserted between the scan-out pin of the last flop in the scan chain clocked by C1, and the scan-in pin of the first flop in the scan-chain clocked by C2. The enable of the latch is connected to C1 such that it is transparent when C1 is low. The latch holds the previous scanned value for the duration when the clock pulse is high. This approach works, provided the skew is not greater than the high pulse width of the clock. Alternatively, one must use DC to insert delays to frx the hold time violations. 

Fig. 7.12 Our SPIRE flow proceeds in phases. First the MILP that represents only static timing analysis is solved without design changes. The vtdues of relevant variables are saved and passed to the next stage which runs an MILP that incorporates retiming and cloning. The retiming variables are saved and fixed in an MILP that allows latches to move. Finally, with known values for latch locations and retiming variables we run the complete linear program...

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