Avoiding Latches

A variable that does not have a value assigned in all branches of a case statement or an if statement can lead to a latch being built. This is because in Verilog HDL, a reg variable (assigned within an always statement) infers memory, and thus if the variable is not assigned a value in all branches of a conditional statement, the value needs to be saved in memory. Here is an example. 

What is the value of Luck when Probe is 0 It must be the old value of Luck. Thus the value of Luck needs to be saved a latch is created for this variable. 

The best way to avoid latches is to first determine from the synthesis tool how many latches have been inferred. A designer now needs to go back and check if each latch inferred really needs to be a latch. It could be that the designer never intended for a latch or the designer forgot to specify values under all conditions. The best rale is to check the latches that get synthesized and go back and determine why each latch got synthesized and fix code if necessary to avoid any unwanted latches. 

Here are two ways of avoiding a latch for the above example. In the first approach, assign a value to the variable in the else branch as well. 

In the second approach, initialize the value of the variable before the if statement. 

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An alternative way to avoid latches in the above example is to specify a default branch in the case statement or to make a default assignment to all variables assigned in a case statement (in this example, NextToggle), prior to the case statement. Here is an example that uses a default branch to avoid inferring latches. 

It is necessary to specify the full case synthesis directive, otherwise latches are inferred for Address. Alternatively, an initial assignment to Address before the case statement can also be made to avoid latches no synthesis directive is then necessary. This is shown in the following always statement. 

The problem with this approach is that since it is impractical to list all possible values an integer can take, to avoid latches either the default case branch must be specified or the full case synthesis directive must be used. Another problem with this approach is not good readability. 

The Cooperative Four State Hypothesis makes the separation of the time-courses of isometric force and maximum shortening velocity easier to understand. Moreover, it avoids the faulty predietions of the Latch Hypothesis described above. 

Arithmetic operations as conditional expressions, as in the previous example, should be avoided when inferring latches since there is a very high probability of race condition between the conditionals in the synthesized netlist this might cause the latched value in the synthesized netlist to differ from that in the Verilog HDL model. 

Discrepancies in terminology. A new lexicon is emerging. The lexicon must be carefully and precisely translated in its application to healthcare to avoid miscommunication. Marketing may ask for a CHA and not know the difference between a CHA and a CEA. They may not understand the approaches, but will only latch on to the buzzwords. 

Train drivers to deal with pressure loaded equipment. Doors that have freight against them, certain types of trailer door latches, chain binders, and strap winches are all examples of equipment that can be pressure loaded. Be sure drivers are aware of the possibility and are trained to diffuse the pressure in such a way as to avoid injury. 

A voltage regulator should be used to isolate the instrument from voltage fluctuations, and the electric supply should be latched to avoid uncontrolled powering up of the apparatus following a power failure. 

Reproducible results are achieved only with a constant environment. Laboratory benches exposed to the sun during part of the day should be avoided because of temperature variation. Most development chambers are of such a size that they may conveniently be placed in an environmentally controlled space, room, or bath as a way of maintaining consistency. It is advisable to weigh down the lid of the chamber so that it cannot be dislodged by vapor pressure or heat produced by the mobile phase, which would disturb the equilibrium within the system. Some newer chambers include latches that actually lock down the lids. 

The data exchange goes through three-state bidirectional transceiver 74LS244 (A65, A72). The data from the upper four lines between transceiver and RAM can be stored in latch 74LS373 (A75) in order to avoid false data registration in some phases of the programme. 

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