Casez statement

In a casez statement, the value z is considered as a don t-care when it appears in a case item expression. The character can also be used alternatively for the character z. Values z and x are not allowed in a case expression. Additionally, value x cannot appear in a case item expression. Here is an example of a casez statement. 

The casez statement is equivalent to the following i f statement (note that the character in a case item denotes a don t-care value). 

The rules for inferring latches apply to casex and casez statements equally as well. 

Verilog HDL semantics of a case statement specifies a priority order in which a case branch is selected. The case expression is checked with the first case item, if it is not the same, the next case item is checked, if not the same, the next case item is checked, and so on. A priority order of case item checking is implied by the case statement. Additionally, in Verilog HDL, it is possible for two or more case item values to be the same or there may be overlapping case item values such as in casex and casez statements however, because of the priority order, only the first one in the listed sequence of case items is selected. 

When value x is used in a case item of a case statement (not casex, casez), the branch corresponding to that case item is considered never to execute for synthesis purposes. 

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