Redundant operators

Circuits shall be separated and segregated to minimize the risk of interference during operation and maintain redundant operation. 

The solution (based on two MV 100 frequency converters) allows a full redundancy operation with no hoist performance limitations. Thus, in case of a converter fails the drive system works in single mode (with one converter) but the full speed, full torque, and overload requirements are maintained, in such a way that service continuity is guaranteed without any performance limitation. 

Lee CC (1983) Elimination of redundant operations for fast sobel operator. IEEE Trans Syst Man Cybern, vol SMC-13, No 3, pp 242-245... 

Uses cleanup rules to eliminate redundant operations in the flowgraph, and optimization rules to replace behavioral constructs with others more closely matching library components. Also uses transformation for loop unwinding and loop pipelining. 

Systolic transformations, plus local transformations (associative and distributive transformations, elimination of redundant operations, etc.). 

EXAMPLE 13-1 BH3, like ammonia, has a three-fold symmetry axis. However, BH3 is planar. As a result, there is an extra symmetry operation—reflection through the molecular plane—that does not move any nuclei. Thus, both the identity operation and this reflection leave all nuclei unmoved. Is this an example of redundant operations ... 

Common sub-expression elimination, where redundant operations that produce the same results are removed. 

The technique at all times tries to minimize the interconnection length along the critical path(s). Once all the operations have been scheduled, a pairwise interchange improvement procedure is executed. Redundant operators which are not required for the minimum feasible design, may be introduced during the improvement process. The redundant operators may be allocated to alleviate interconnection delays along the critical path. Interconnection delay is estimated by a first-order equation. 

For comparison purposes, we linearly scaled down each functional unit area and delay from 3-micron process parameters. We used different device parameters for different fabrication processes to calculate wiring delay in this program. Our experiments shows interconnection delay time contributes 20% of functional unit delay to overall delay with 1.6 micron fabrication process. The overall delay time could be reduced to 5% above functional delay by introducing redundant operators along the critical path. 

For finer feature sizes, the interconnection delay plays a more important role, due to more complex designs fitting into one chip and the higher system performance required. Redundant operator allocation becomes a feasible solution due to the smaller area of operators. Our predictions show the interconnection delays will become dominant when submicron fabrication process are used. 

The summation in (12.2.6) should be interpreted as involving only the nonredundant orbital rotations. A discussion of Hartree-Fock orbital redundancies was given in Section 10.1.2. In MCSCF theory, the question of orbital redundancies is more difficult because of the coupling to the configuration space. The MCSCF redundancies are therefore considered in more detail in Section 12.2.6, where we develop a set of simple conditions that allow us to identify the redundant operators in (12.2.6). 

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