Back-annotation

Next is the layout of the micromechanical and electronic parts of the system. Even at this stage changes are being made, which need to be back-annotated to the component level and also to the system level, if necessary. In electronics, for example, the back-annotated parameters are the specific capacitances, which are not known before layout. In mechanical micromachining, the specific parameters include capacitances as well as masses, moments of inertia, thermal capacities, and conductivities. 

Subsequently, the mechanics and electronics are laid out. During layout, electrical and mechanical properties may change once more. Therefore, we have to perform back-annotation again to verify the system s behavior. 

Produce tables containing information required for device programming and back annotate interconnection neflists. Back annotation provides information about interconnection paths and fanout that is necessary to produce accurate timing estimates during simulation. 

Back-annotate physical information from placement in the Floorplan Manager. Create custom wire-load models for your design based on the back-annotated data. This wire-load can be based on physical grouping performed during step 2. 

Repeat steps 2, 3 and 4 until the design meets timing with sufficient slack. Then proceed to perform complete routing and generate back-annotation data in SDF, PDEF and parasitics (set load/seat resistance)... 

Example 6.4 shows net resistance and net parasitic file written out from a commercial Florrplanning tool. In other words, the tool provides estimated resistance and capacitance values for each net in the design. This information can be back-annotated to DC to generate new more accurate wire load models as discussed in section 6.4 or to perform in place optimization. 

Creating Wire Load Models After Back-Annotation... 

Include script with back annotation information, that is, a dc shell sct joad script with load information for all nets in the design and an SDF file. 

You are doing post-route static timing analysis using SDF file generated from layout tools. Do wire load models affect the timing after back-annotation You get different results for different wire load models. 

If the tool that generated the SDF file lumped the transition delay in with the net delay rather than the cell delay (DC assumes that the transition time is by default included in the cell delay), and if you have not back annotated your capacitance information as well, then when DesignTime tries to subtract the transition delay from the net delay it must base the calculations of transition delay on the wire load model. Wl-r vou read the back annotated timing, you should set the two variables if the trans time has been included in the net delay. 

If you set the above variables, DC calculates the transition delay and ts it from the net delay and adds it to the cell delay. It uses the back annotated v. jtances to calculate the transition delay. However, if you don t back annotate your capacitances, DC must use the capacitances in the wire load model. This might explain the differences you saw with different wire load models after back annotating the timing. 

DC supports the following SDF timing constructs for forward annotation to simulation tools and back-annotation from back-end tools ... 

You have back annotated an SDF delay file which contained min/max/typ values into DC. But the timing reports generated by the report timing command are identical for min or max timings. 

DC reads only one set of values from the SDF file each time a iile is back annotated. The following variables need to be set to indicate which set of values should be read ... 

These variables can be set to a value of minimum, maximum, or typical. To get different timing reports for the min and max values, back-annotation needs to be repeated for min or max values. 

When back annotating values into Synopsys, the wire load model is taken into account. If the values written out from the initial design also contain the WLM, is there a way to specify no wire-load model in DC ... 

For in place optimization, often back annotated information after P R is in the form of set load script. After including these set load information, it might be required to find all the nets which have load values set and all the nets which do not. Then for all those without load values, it might be required to set specific load value. The following script can be used to do this. 

Finally, a timing simulation needs to be performed when the technology net-list has been placed and routed and the timing information is back-annotated to the design to include wiring delays. 

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