Three-dimensional Integrated Circuits

The drawback of organic transistor-based sheet image scanners so far, which has been a serious bottleneck in practical applications, has been the slow operating frequency. To overcome this problem we have used a new circuit concept, double 

Photograph of fabricated scanner system and cross-sectional view. 

In the future it is supposed that the number of pixels per word-line and bit-line will be increased to more than 2048, and pixel size is reduced to less than 1/16. The delay for the conventional scheme will be of the order of 103 s whereas the proposed double word-line/bit-line scheme using stacked organic transistor sheets is estimated to reduce the delay by several order of magnitude. Power consumption 

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Rahman A, Fan A, Chung J, Reif R. Wire-length distribution of three-dimensional integrated circuits. IEEE International Interconnect Technology Conference 1999.p 233-235. 

Warner K, Chen C, D Onofrio R, Keast C, Poesse S. An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication. Proceedings of The IEEE International SOI Conference 2004. p 71-72. 

Patti R. Three-dimensional integrated circuits and the future of system-on-chip designs. Proceedings of the IEEE 2006 94 (No. 6) 1214-1222. 

Burns J, Mcllrath L, Keast C, Loomis A, Warner K, Wyatt P. Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip. Proc IEEE ISSCC 2001 453 268-269. 

Wilkerson P, Raman A, Turowski M. Fast, automated thermal simulation of three-dimensional integrated circuits. In Proceedings of Inter Society Conference on Thermal Phenomena 2004. p 706-713. 

M. Chan. The potential and realization of multi-layers three-dimensional integrated circuit. Int l Solid-State and Integrated-Circuit Technology, 2001, 40 - 45. 

S. M. Alam, D. E. Troxel, C. V. Thompson. A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits. In Proc. IntT Sym m on Quality Electronic Design, 2002, pp. 246 - 251. 

S. Das. Design automation and analysis of three-dimensional integrated circuits. Ph. D. dissertation, Department of Electrical and Computer Science, MIT, May 14, 2004. 

Low-temperature aluminum-germanium (Al-Ge) eutectic bonding at a low temperature of 435 °C has been investigated for monolithic three-dimensional integrated circuit (3DIQ applications (Cmogorac et al. 2009). 

Figure 11.16. Overview of 3D NW circuit integration, (a) Contact printing of NWs from growth substrate to prepatterned substrate, (b) Three-dimensional NW circuit is fabricated by the repetition of the contact printing, device fabrication, and separation layer deposition steps N times. [Reprinted with permission from Ref.75. Copyright 2007 American Chemical Society.] (See color insert.)...

Stacked planar optics, a new concept in integrating optical circuits, has been proposed. By using stacked planar optics, we not only make possible the monolithic fabrication of optical circuits, such as the directional coupler and wavelength demultiplexer, but we can also construct three-dimensional optical circuits by allowing coupling among individual components in the array with a suitable design. 

Deep recesses, holes, and other difficult three-dimensional configurations can usually be coated with relative ease. For instance, integrated circuit via holes with an aspect ratio of 10 1 can be completely filled with CVD tungsten. 

MOSFETs. The metal-oxide-semiconductor field effect transistor (MOSFET or MOS transistor) (8) is the most important device for very-large-scale integrated circuits, and it is used extensively in memories and microprocessors. MOSFETs consume little power and can be scaled down readily. The process technology for MOSFETs is typically less complex than that for bipolar devices. Figure 12 shows a three-dimensional view of an n-channel MOS (NMOS) transistor and a schematic cross section. The device can be viewed as two p-n junctions separated by a MOS capacitor that consists of a p-type semiconductor with an oxide film and a metal film on top of the oxide. 

The constant drive to miniaturize components for communications devices is stimulating efforts to develop LTCC technology into three dimensional circuitry in which passive components (resistors, capacitors and inductors) are packaged into the structure with the active, integrated circuits, bonded to the outer surface. The technology is reviewed by W. Wersing et al. [18]. 

An integrated circuit is a multilayer, three-dimensional structure of electrically interconnected solid-state circuit elements isolated with patterned dielectric films. The dielectric, conductor, and semiconductor films are deposited or formed by sophisticated chemical reactions. The successful growth and manipulation of these films depend heavily on the proper design of chemical reactors used in deposition and etching, the choice of appropriate chemical reagents, separation and ultrapurification, and operation of sophisticated control systems. 

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