Thin silicon nitride

Figure 3.48 Exploded schematic view of a flow-cell FPW liquid sensor. The silicon chip containing die thin silicon-nitride membrane, piezoelectric film and transducers is sandwiched between two etched silicon chips. The upper chip is a cap with fluid inlet and outlet fittings, b also provides vias for contact to a temperature-sensing polysilicon resistor deposited on the FPW chip below it. The lower chip introduces transducer contact leads and protects the underside of the membrane fitm contact with the fluid. (Hgwc courtesy of Beo Costello, Bokeley Microliulratitents, Inc.)...

New, alternative methods for membrane preparation are also reported in the literature. For example, the membrane microsieves with a very regular pore structure (pores from several micrometers down to 0.1-0.2 pm) are prepared via photolithography [101,102]. These very thin silicon nitride membranes combine a very high porosity with extremely high permeabilities, much larger than the track-etched or other microfiltration membranes with similar pore size. 

Figure 5.12. IR transmission spectmm of thin silicon nitride film produced by CVD of SiH4 + N2 at 65°C. Reprinted, by permission, from T. Inukai and K. Ono, Jpn. J. Appl. Phys. 33, 2593 (1994). Copyright 1994 Publication Board of Japanese Journal of Applied Physics.

The market for silicon nitride is fast growing, particularly in structural and chemical resistance applications and as a thin film in semiconductor devices.P 1... 

Thin films of electrical insulators are essential elements in the design and fabrication of electronic components. The most widely used insulator materials (dielectrics) are silicon oxide (Si02) and silicon nitride (Si3N4). These materials are extensively produced by CVD. 

Electrochemical experiments have been carried out on materials deposited by PVD on silicon microfabricated arrays of Au pad electrodes [Guerin et al., 2006a]. The substrate is made up of a square silicon wafer capped with silicon nitride (31.8 mm x 31.8 mm), which has an array of 100 individually addressable Au pad electrodes. These electrodes make up a square matrix on the wafer, which can be masked when placed in a PVD chamber, allowing deposition of thin films on the Au electrodes. Figure 16.3 is a schematic drawing of the configuration. Small electrical contact pads in Au for the individual addressing of electrodes (0.8 mm x 0.8 mm) are placed on the boundaries. 

J. Sun, N. Lindvall, M.T. Cole, K.B.K. Teo, A. Yurgens, Large-area uniform graphene-like thin films grown by chemical vapor deposition directly on silicon nitride, Applied Physics Letters, 98 (2011) 252107. 

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

The rapid developments in the microelectronics industry over the last three decades have motivated extensive studies in thin-film semiconductor materials and their implementation in electronic and optoelectronic devices. Semiconductor devices are made by depositing thin single-crystal layers of semiconductor material on the surface of single-crystal substrates. For instance, a common method of manufacturing an MOS (metal-oxide semiconductor) transistor involves the steps of forming a silicon nitride film on a central portion of a P-type silicon substrate. When the film and substrate lattice parameters differ by more than a trivial amount (1 to 2%), the mismatch can be accommodated by elastic strain in the layer as it grows. This is the basis of strained layer heteroepitaxy. 

This approach allows the deposition of thin films at low temperatures. By comparison, polymer deposition generally requires very high temperatures. For instance, the chemical vapor deposition of silicon nitride requires a temperature of about 900°C, whereas the plasma chemical deposition requires a temperature of only 350°C. 

---