SRAM cell

Nakabayashi T, Uehara T, Segawa M, Ukeda T, Yamanaka M, Yamada T, Arai M, Yabu T, Yamashita K, Kobayashi S, Murakami T, Saeki M, Okuyama H, Kanda A, Ogura M. A novel 0.25 pm CMOS technology for 6. 82 pm 6-Tr. SRAM cell with elevated trench isolation and line-and-space shaped gates (ETILS). lEDM Technical Digest Dec 1995. p 1011-1013. 

FIGURE 20.6 SRAM-cell size is a key metric of scaling for microprocessor technologies. Intel Corp. maintains a 50 % aerial shrink of SRAM cell with each technology (a). 45-nm technology SRAM cell (b) is the latest addition to the trend. The dotted line represents the six transistor cell—horizontal lines are the MOS gates and the vertical lines are diffusion regions (from Ref 5). 

Polyimide tape, die and wire bond, over-mold Near CSP FBGA-T (ChipPAC) DSPs, memory products, ASICs, and SRAMs, cell phones, and pagers... 

Figure 8.53 gives the circuit of a complete SRAM circuit design with only one column and one row shown. One of the key design parameters of a SRAM cell is to determine the size of transistors used in the memory cell. We first need to determine the criteria used in sizing transistors in a CMOS 6-transistor/cell SRAM. 

FIGURE 8.52 Different SRAM cells (a) six-transistor SRAM cell with depletion transistor load, (b) four-transistor SRAM cell with polyresistor load, (c) CMOS six-transistor SRAM cell, (d) five-transistor SRAM cell. 

FIGURE 8.54 Multiported CMOS SRAM cell (shown with 2-read and 1-write). 

FIGURE 8.55 Layout example of four abutted 6-t SRAM cells. 

Depending on the state of the SRAM cell (a T or 0 in the memory) the mirror is electrostatically attracted by a combination of the bias and address voltage to one or the other of the address electrodes. The mirror rotates until its tip touches on a landing electrode fabricated from the same level of metal as the electrode. The electrode is held to the same potential as the mirror. The mirror can rotate +/- 10°. A T in the memory causes the mirror to rotate while a 0 in the memory causes the mirror to... 

Nowak, E.J., B.A. Rainey, D.M. Fried, J. Kedzierski, M. leong, W. Leipold, J. Wright, M. Breitwisch. 2002. A functional FinFET-DGCMOS SRAM cell. International Electron Devices Meeting Technical Digest 411—414. 

Hada H, Amanuma K, et al (2004) Capacitor-on-metal/via-stacked-plug (CMVP) memory cell technologies and application to a nonvolatile SRAM. Ferroelectric Random Access Memories Fundamentals and Applications 93, 215-232... 

Fig. 3. Experimental demonstration of one-, two- and three-transistor logic circuits with CNTFETs [41]. Output voltages as a function of the input voltage are given for (A) an inverter, (B) a NOR gate, (C) a static random access memory cell (SRAM) and (D) a ring oscillator.

Sram (207) gave Chinese hamsters dlectqrlaalnoethyl benzllate Intraperltoneally at 0.1, 1, and 10 mg/kg. The animals were killed 24 h later, and the cells of their bone marrow were examined for chromosomal abnormalities. The lowest dose of the benzllate did not give rise to any detectable chromosomal abnormalities 1 mg/kg resulted In a 50% Increase... 

Techniques based on space redimdancy are grounded in the single fault model, where only one of the hardware redimdant copies is affected by transient upsets (ROSSI 2005). It means that only one of the modules will be affected by a transient fault and therefore the fault detection rate should be 100 %. On the other hand, studies have shown that a single fault may affect two hardware modules in case of SRAM-based FPGAs (KASTENSMIDT 2005) due to the routing of the architecture, or in adjacent standard cells in ASICs, as shown by Almeida (ALMEIDA 2012). 

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