SRAM-based FPGA

Table 4.7 Partial reconfiguration time for SRAM-based FPGA (Vttlex 4 xc4vlx80- 12fril48) 51...

Table 7.2 Fault injection by partial reconfiguration in SRAM-based FPGA 84...

Soft errors can be detected and corrected by the system s logic, meaning that it does not require a hard reset to recover from an error. Sections 7.1.2 and 7.2.2 present neutron irradiation experiments simulating the effect of SEE in Flash-base and SRAM-based FPGAs, while Chaps. 5 and 6 present fault injection simulation experiments simulating SEEs at RTL level and in the configuration memoiy bitstream, respectively. In this work, SEUs and SETs will be used to describe transient faults that the proposed techniques can cope with. 

Techniques based on space redimdancy are grounded in the single fault model, where only one of the hardware redimdant copies is affected by transient upsets (ROSSI 2005). It means that only one of the modules will be affected by a transient fault and therefore the fault detection rate should be 100 %. On the other hand, studies have shown that a single fault may affect two hardware modules in case of SRAM-based FPGAs (KASTENSMIDT 2005) due to the routing of the architecture, or in adjacent standard cells in ASICs, as shown by Almeida (ALMEIDA 2012). 

Table 4.7 shows the time required to partially reprogram each OCFCM on a SRAM-based FPGA. As one can see, the time varied from 8.1 nrs to 9.9 nrs. This value is directly proportional to the size of each OCFCM. The recorrfiguration is orrly necessary when the module is not implemented on the board, meaning that it is rrot required when using the architecture shown in Fig. 4.11. 

SRAM-based FPGA (Virtex 4 xc4vlx80-12ffll48) Flash-based FPGA (ProAsicS 1500)... 

In order to perform the experiments presented in this Chapter, we implemented the miniMIPS hardened with the novel hybrid HETA technique and the software-based techniques Variables and Inverted Branches on both flash-based and SRAM-based FPGAs. We visited three facilities, used two types of energetio particles, and performed tests for SEE and TID. In the following, each radiation experiment and its results are diseussed in detail. 

In the following, a irradiation experiment on SRAM-based FPGAs is described. 

This irradiation experiment was performed at the LANSCE facility, in Los Alamos, USA. We implemented the miniMIPS mieroprocessor in a Vntex5 SRAM-based FPGA, part XC5VLX110T. The main goal was to check the response of HETA when applied to SEEs in SRAM-based FPGAs. 

KASTENSMIDT, E STERPONE, L. CARRO, L. SONZA REORDA, M. On the optimal design of triple modular redundancy logic for SRAM-based FPGAs. In DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE, 2005, DATE 2005. Proceedings... New York, USA ACM Press, 2005, pp. 1290-1295. 

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