Transient fault

The instant (sub-transient) fault current, /jjgf, through a generator in a symmetrical three-phase system, irrespective of the condition of neutral as defined in Table 13.9 will be... 

The following discussion and worked example for an LNG plant show how to carry out simple but reasonably accurate estimates of the sub-transient fault current and its decay in the first few cycles. Following is a discussion on how to assess the fault breaking current. 

The method adopted below is based upon the principles set out in IEC60363 and 1EC60909, both of which describe how to calculate sub-transient and transient fault currents, and are well suited to oil industry power systems. The method will use the per-unit system of parameters and variables. Choose the base MVA to be Nbase-... 

Many power system networks can be reduced to a simple series-connected circuit containing a resistance R and an inductance L, for the purpose of calculating the transient fault current. Furthermore a... 

The total of these currents is the peak asymmetrical sub-transient fault current which is 61,375 amps. This is a conservative summation because it assumes that the three peaks occur at the same time. The fault making duty of the main switchboard must be greater than this value of current,... 

IEC60363 was first available in 1972 and IEC60909 in 1988. 1EC60363 was issued for evaluating the short circuits in power systems that are used onboard ships. It covers both the transient and sub-transient fault situations. AC power systems on modern large ships have certain similarities to those in oil industry, marine and onshore installations, e.g. 

Significant contribution of sub-transient fault current from induction motor consumers. 

Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors... 

J. R. Azambuja et al.. Hybrid Faith Tolerance Techniques to Detect Transient Faults in Embedded Processors, DOI 10.1007/978-3-319-06340-9 l,... 

Soft errors can be detected and corrected by the system s logic, meaning that it does not require a hard reset to recover from an error. Sections 7.1.2 and 7.2.2 present neutron irradiation experiments simulating the effect of SEE in Flash-base and SRAM-based FPGAs, while Chaps. 5 and 6 present fault injection simulation experiments simulating SEEs at RTL level and in the configuration memoiy bitstream, respectively. In this work, SEUs and SETs will be used to describe transient faults that the proposed techniques can cope with. 

Techniques based on space redimdancy are grounded in the single fault model, where only one of the hardware redimdant copies is affected by transient upsets (ROSSI 2005). It means that only one of the modules will be affected by a transient fault and therefore the fault detection rate should be 100 %. On the other hand, studies have shown that a single fault may affect two hardware modules in case of SRAM-based FPGAs (KASTENSMIDT 2005) due to the routing of the architecture, or in adjacent standard cells in ASICs, as shown by Almeida (ALMEIDA 2012). 

In the following sections, we will present the HPCT tool to automatically transform program codes into hardened ones, two known software-based techniques, called Variables and Inverted Branches, and three novel hybrid techniques to detect transient faults in embedded processors, named PODER, OCFCM, and HETA, combined with the previous known software-based techniques. 

As one can see in Table 5.3, from the total amorrrrt of faults injected, around 20 % affected the system arrd cairsed an error in the firral result. When protected by the OCFCM techniqrres, 100% of the faults were detected. In order to confirm these results, we injected another 140,000 faults in the PC (which is the most sensitive area of the microprocessor with respect to control flow errors) of the bubble sort application, due to its low execution time and got 100% fault detection. These results mean that the studied hardening approach was able to fully protect the microprocessor system, by detecting every transient fault injected in the case-study appUcatiorrs. Aside from these results, an average of 1 % faults with no errors per application was detected. 

The chosen embedded system was composed of a MIPS microprocessor hardened with HETA, an unhardened SRAM memory embedded in the FPGA, two SpW links (TARRILLO 2011) and the FPGA embedded Phase-Locked Loop (PLL) clock module. The system has some fault tolerant capabilities that are able to detect transient faults, but not necessary TID effects as radiation results will show. Figure 7.1 shows the architecture of the embedded system. 

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