Simulation fault injection

Table 5.3 Number of faults injected by simulation fault injection in miniMIPS protected by OCFCM and the percentage of detected errors 67...

Although the effect of faults is increasing, the rate is not yet sufficient to test fault tolerant techniques at ground level. In order to do so, fault emulation and testing is necessary. In this Section, we will go over a few options to do so, such a software fault injection by simulation, fault injection in the FPGA s memory configuration bitstream and irradiation experiments. 

In the following, we describe the simulation fault injection campaign for each technique. 

Analysis of fault effects requires detailed information on the faults injected and the application behaviour. FITS provides details about every test (simulated fault injection). Hence, manual replay of the whole test execution can be done. Moreover, all the events and user messages occurring during the test are recorded. The tested application is instrumented to save its outputs (here simulation results, i.e. a set of process signals (u u, y y ) in subsequent sampling instants) into separate files for each test (file names managed by fault injectors). This gives a possibility for post-experiment analysis of fault effects in the correlation with the injected fault and observed behaviour for each test (see Sect. 5). 

Stott, D.T., Ries, G., Hsueh, M.C., Iyer, R.K. Dependability Analysis of a High-Speed Network Using Software-Implemented Fault Injection and Simulated Fault Injection. IEEE Transactions on Computers 47(1), 108-119 (1998)... 

A Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded... 

Keywords Simulated Fault Injection, Automatic Test Executor, Time-Triggered Systems, Dependable Systems, Safety-Critical Systems, Fault Tolerance. 

Simulated Fault Injection (SFI) is a technique to insert faults in models of systems during their simulation. This technique allows the developers to observe the behavior of the system in the presence of faults, enabling the verification of fault-tolerance mechanisms before assembling a system prototype. The analysis of the results obtained in SFI campaigns can be used to evaluate the effectiveness of the fault tolerance mechanisms, analyze the weaknesses of the system and study possible improvements. 

Given this situation, the aim of this research work is to provide a modeling and simulation environment for dependable Time-Triggered HW/SW systems based on SystemC. The main contribution of this paper is the presentation of a testing and simulated fault injection framework for the Platform Specific Time-Triggered Model (PS-TTM) approach [2], which enables reproducible non-intrusive SFI at different stages of the development for the early assessment of fault-tolerance mechanisms. 

The paper is structured as follows Section 2 briefly describes previous related work. Section 3 reviews the PS-TTM modeling and simulation platform for dependable time-triggered embedded systems, which is the platform where the testing and fault injection framework has been developed. Section 4 presents the framework for the verification of time-triggered dependable systems by simulated fault injection at different stages of the development, which is evaluated in Section 5 by means of a case study based on a simplified railway signaling system. Section 6 briefly presents the results obtained in the case study and finally Section 7 summarizes the main conclusions of the work. 

The PS-TTM simulation platform has been extended with facilities to perform testing and simulated fault injection experiments. Two are the main aims of this... 

In order to check the testing and simulated fault injection fi amework described in Section 4, we model a simphfied railway signaling system by means of the PS-TTM platform. Following the approach described in the PS-TTM, we first design a PIM and we later refine it into a PSM. 

This section describes the reliability assessment made to the railway signaling system model described in Section 5. The fault-tolerance provided by the system is evaluated by means of simulated fault injection. To do so, the PS-TTM ATE framework described in Section 4 is connected to the SUT and the environment model as shown in Fig. 4. 

This paper introduced a testing and simulated fault injection framework for time-triggered dependable-systems based on the PS-TTM approach. The environment enables testing and injecting faults at different stages of the design, from platform independent models to platform specific models, what enables an early detection of design flaws in the system. 

Ayestaran, I., Nicolas, C.F., Perez, J., Larrucea, A., Puschner, P. Modeling and Simulated Fault Injection for Time-Triggered Safety-Critical Embedded Systems. In IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, ISORC (2014)... 

Perez, J., Azkarate-askasua, M., Perez, A. Codesign and Simulated Fault Injection of Safety-Critical Embedded Systems Using SystemC. In European Dependable Computing Conference, p. 9 (2010)... 

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