Silicon-on-insulator substrate

Nagano, T., Ishikawa, Y., and Shibata, N. Preparation of silicon-on-insulator substrate on large free-standing carbon nanotube film formation by surface decomposition of SiC film. Jpn. J. Appl. Phys. 42, 2003 1717-1721. 

Geear et al. of Microsaic Systems [7] has demonstrated a more advanced MEMS quadrupole. The device is formed from two bonded silicon-on-insulator substrates, which... 

Sophisticated nanolectronic devices such as SiNW transistors and circuits have been fabricated by AFM oxidation nano-lithography. In this application, AFM oxidation generates a narrow oxide mask on top of the active layer of a silicon-on-insulator substrate. The unmasked silicon layer is then removed by using... 

Figure 11.11. Integration of nanowire photonics with silicon electronics. Schematic illustrating fabrication of hybrid structures. A silicon-on-insulator (SOI) substrate is patterned by standard electron-beam or photolithography followed by reactive ion etching. Emissive NWs are then aligned onto the patterned SOI substrate to form photonic sources. [Reprinted with permission from Ref. 59. Copyright 2005 Wiley-VCH Verlag.]...

Progress in semiconductor processing has evolved in a number of substrate materials, pre-destined for the use in micro structured devices, such as Silicon, Silicon-on-Insulator (SOI), Silicon Carbide and Gallium Arsenide [1]. 

SOI Silicon on Insulator material is today s most advanced Silicon-based substrate technology it is basically Silicon material with an integrated insulation layer underneath a single crystal Si layer. It combines most of the advantages of the most well established Silicon technology with high radiation, media and temperature compatibility. 

Substrates The substrates in microelectronics are mainly Si wafers. For mobile applications, silicon-on-insulator (SOI) wafers increasingly replace bulk Si wafers and for very specific high-frequency applications, III-V compound semiconductors (e.g., GaAs) are used. The majority of substrates in microfabrication are Si wafers, but metal, glass, and ceramic substrates are also common. Particularly when using glass, quartz, and ceramic wafers in CMP processes, it has to be taken into account that they are brittle and easy to break. The situation is worse when the material is also under stress induced by deposited layers. For applications where the backside of the wafer has to be structured (e.g., in bulk micromachining), double-side polished substrates are employed. 

Application In order to change the physical, chemical, or electrical properties of the solid substrate, ion implantation technique has been widely used in semiconductor device manufacturing and in metal finishing, for example, semiconductor doping, silicon on insulator (SOI) substrates preparation, and steel toughening. 

To make the 2 nm Si02 nanopores, the typical process starts with a silicon-on-insulator (SOI) wafer. The silicon substrate is anisotropi-cally etched by KOH to leave a small region of freestanding silicon film. E-beam lithography is then performed to create a hole in the device silicon layer, and the size of the hole is further reduced by thermal oxidation to grow a layer of Si02 from the device layer silicon. This process will lead to a nanopore of less than 20 nm diameter, which is subsequently shrunk to 2-3 nm in a transmission electron microscope by focus electron beam-mediated reflow of the Si02. 

An advantage of epitaxy is the high growth rate of material, which allows the formation of films with considerable thickness (>100 /itm). Epitaxy is a widely used technology for producing silicon on insulator (SOI) substrates. The technology is primarily used for deposition of silicon. 

Wafer bonding is a technology to combine two substrates in order to achieve a mechanically stable connection between them. The technology is apphed for substrate production, for example, for the fabrication of silicon on insulator wafers or compound semiconductor wafers and for device fabrication, for example, for the fabrication of MEMS/MOEMS devices as described in previous sections, for stacking devices in 3D integration, or for wafer-level packaging. 

Another limitation is the need to isolate devices from each other (Brews, 1990 Chen, 1990, Einspruch and Gildenblat, 1989 Pimbley et al., 1989 Wolf, 1995), so that their actions remain uncoupled by parasitics. As isolation structures are reduced in size to increase device densities, new parasitics are discovered. A solution to this problem is the manufacture of circuits on insulating substrates, silicon-on-insulator... 

Step 1 We start by choosing a suitable substrate—a silicon-on-insulator (SOI) wafer. An SOI wafer consists of a thin (1 pm or less) Si02 layer sandwiched between two Si layers. We first thermally grow 1 pm of Si02. 

---